SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The CC23xx device controller includes the Arm NVIC. The NVIC and Arm Cortex M0+ prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The processor supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set priority/preemption grouping in eight levels on internal CPU exceptions and interrupts.
Features of the NVIC include: