The Motorola SPI is a 4-wire interface where the CS signal behaves as a peripheral select. In the 3-wire mode the CS signal is not required and the module behaves as if always selected. The main feature of the Motorola SPI format is that the inactive state and phase of the SCLK signal can be programmed through the SPO and SPH bits in the SPI.CTL0 control register.

SPO Clock Polarity Bit

If the SPI.CTL0[8] SPO clock polarity control bit is cleared, the SCLK pin outputs a steady-state low value when data is not being transferred. If the SPI.CTL0[8] SPO bit is set, the SCLK pin outputs a steady-state high value when data is not being transferred.

SPH Phase-Control Bit

The SPI.CTL0[9] SPH phase-control bit selects the clock edge that captures data. The state of this bit has the most impact on the first bit transmitted, by either allowing or not allowing a clock transition before the first data capture edge. If the SPI.CTL0[9] SPH phase-control bit is cleared, data is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.

Motorola SPI Frame Format with SPO = 0 and SPH = 0

Figure 20-2 shows signal sequences for Motorola SPI format with SPO = 0 and SPH = 0.

In this configuration, the following occurs during idle periods:

• SCLK is forced low
• CS is forced high
• The transmit data line PICO is forced low
• When the SPI is configured as a controller, the SCLK pin is enabled
• When the SPI is configured as a peripheral, the SCLK pin is disabled

If the SPI is enabled and valid data is in the TX FIFO, the CS controller signal is driven low at the start of transmission which causes enabling of peripheral data onto the POCI input line of the controller. The controller PICO output pin is enabled.

One-half SCLK period later, valid controller data is transferred to the PICO pin. Once both the controller and peripheral data is set, the SCLK controller clock pin goes high after an additional one-half SCLK period. The data is now captured on the rising edges and propagated on the falling edges of the SCLK signal.

For a single-word transmission after all bits of the data frame are transferred, the CS line is returned to the IDLE high state one SCLK period after the last bit is captured. For continuous back-to-back transmissions, the CS signal must pulse high between each data word transfer because the peripheral-select pin freezes the data in the serial peripheral register and does not allow altering of the data if the SPH bit is clear. The controller device must raise the CS pin of the peripheral device between each data transfer to enable the serial peripheral data write. SPI.CTL0[10] HWCSN described in Section 20.3.6 can be used to override this behavior. When the continuous transfer completes, the CS pin is returned to the IDLE state one SCLK period after the last bit is captured.

Motorola SPI Frame Format with SPO = 0 and SPH = 1

Figure 20-3 shows the signal sequence for Motorola SPI format with SPO = 0 and SPH = 1.

If the SPI is enabled and valid data is in the TX FIFO, the CS controller signal goes low at the start of transmission. The controller PICO output is enabled. After an additional one-half SCLK period, both controller and peripheral valid data are enabled onto their respective transmission lines. At the same time, SCLK is enabled with a rising-edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SCLK signal.

For a single-word transfer, after all bits are transferred, the CS line is returned to the IDLE high state one SCLK period after the last bit is captured. For continuous back-to-back transfers, the CS pin is held low between successive data words and terminates like a single-word transfer.

Motorola SPI Frame Format with SPO = 1 and SPH = 0

Figure 20-4 shows signal sequences for Motorola SPI format with SPO = 1 and SPH = 0.

In this configuration, the following occurs during idle periods:

• SCLK is forced high
• CS is forced high
• The transmit data line PICO is forced low
• When the SPI is configured as a controller, the SCLK pin is enabled
• When the SPI is configured as a peripheral, the SCLK pin is disabled

If the SPI is enabled and valid data is in the TX FIFO, the SPI CS controller signal goes low at the start of transmission and transfers peripheral data onto the POCI line of the controller immediately. The controller PICO output pin is enabled.

One-half SCLK period later, valid controller data is transferred to the PICO line. When both the controller and peripheral data have been set, the SCLK controller clock pin becomes low after one additional half SCLK period. Data is captured on the falling edges and propagated on the rising edges of the SCLK signal.

For a single-word transmission after all bits of the data word are transferred, the CS line is returned to the IDLE high state one SCLK period after the last bit is captured. For continuous back-to-back transmissions, the CS signal must pulse high between each data word transfer as the peripheral-select pin freezes the data in the serial peripheral register and keeps it from being altered if the SPH bit is clear. The controller device must raise the CS pin of the peripheral device between each data transfer to enable the serial peripheral data write. SPI.CTL0[10] HWCSN described in Section 20.3.6 can be used to override this behavior. When the continuous transfer completes, the CS pin returns to its IDLE state one SCLK period after the last bit is captured.

Motorola SPI Frame Format with SPO = 1 and SPH = 1

Figure 20-5 shows the signal sequence for Motorola SPI format with SPO = 1 and SPH = 1.

In this configuration, the following occurs during idle periods:

• SCLK is forced high
• CS is forced high
• The transmit data line PICO is forced low
• When the SPI is configured as a controller, the SCLK pin is enabled
• When the SPI is configured as a peripheral, the SCLK pin is disabled

If the SPI is enabled and valid data is in the TX FIFO, the start of transmission is signified by the CS controller signal going low. The controller PICO output pin is enabled. After an additional one-half SCLK period, both controller and peripheral data are enabled onto their respective transmission lines. At the same time, SCLK is enabled with a falling-edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SCLK signal.

For a single word transmission, after all bits are transferred, the CS line returns to its IDLE high state one SCLK period after the last bit is captured. For continuous back-to-back transmissions, the CS pin remains in its active low state until the final bit of the last word is captured and then returns to its IDLE state. For continuous back-to-back transfers, the CS pin is held low between successive data words and terminates like a single-word transfer.

The serial clock (SCLK) is held inactive while the SPI is idle and SCLK transitions at the programmed frequency only during active transmission or reception of data. The IDLE state of SCLK provides a receive timeout indication that occurs when the RX FIFO still contains data after a timeout period.