SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
DCDC buck converter is a switch mode power supply which generates regulated output voltage from higher unregulated supply. Compared to linear regulators, DCDC has a higher power efficiency which reduces total energy consumption of the SoC.
DCDC is connected in parallel with a linear regulator (GLDO), in the CC23xx implementation.
DCDC supports a maximum load current of around 45 mA when configured to the maximum value. GLDO can support a peak load current up to approximately 55 mA. In applications where higher load current needs are to be met, GLDO is enabled automatically preventing VDDR output going low. The best possible power efficiency is achieved across load variations with the parallel operation of DCDC and GLDO.
The input supply of DCDC can range from 2.2 V to 3.8 V. DCDC regulates the output to 1.5 V. But for GLDO, the supply can range from 1.71 V to 3.8 V to generate a regulated output of 1.5V. DCDC hardware is designed so that when the supply voltage drops below 2.2 V, DCDC automatically shuts off and only GLDO generates the regulated VDDR.
GLDO can operate independently, but DCDC needs GLDO to support driving a higher load above the DCDC limit.
DCDC hardware implements these features to provide smooth and parallel operation of DCDC and GLDO:
Load meter:
Load meter is used to measure load on DCDC output as a percentage of maximum load support by DCDC. Load meter can be enabled by PMUD.DCDCCFG.LM_EN and the output is available on status register PMUD.DCDCSTAT.LOAD. After the load meter feature is enabled, it takes approximately 500 µs to generate the first output, and for any subsequent load change it can take approximately 250 us to update the register to the accurate load level.
GLDO enable toggle logic:
GLDO enable toggle logic is used for parallel operation of DCDC and GLDO. As load increases on VDDR above DCDC load support, GLDO is enabled by analog circuit almost instantly. This feature is used prevent undesirable and repeated enable and disable toggles of GLDO when load on VDDR is close to maximum DCDC load support, which can result in a higher VDDR ripple.
This feature also enables the load meter. Once GLDO is enabled due to higher VDDR load, load meter output is continuously compared with an internally programmed DCDC load threshold. Once the load on DCDC is less than the threshold, GLDO is safely disabled. The hardware also provides a minimum enable window for GLDO to reduce the ripples on VDDR.
Adaptive peak current control:
DCDC has programmable peak current to vary the maximum load support. To support higher load, DCDC can be programmed to higher peak current setting, but then DCDC operates on a reduced power efficiency. With lower peak current DCDC works with higher efficiency but with lower maximum load support. So, for given load on VDDR, there is an optimum peak current setting for DCDC which provides the best power efficiency. Adaptive peak current control is an algorithm which updates peak current dynamically until the optimum value is reached.
For the operation of Adaptive peak current control, load meter output is continuously monitored against two programmable DCDC load thresholds (high threshold and low threshold). If the load on DCDC is more than the high threshold, the algorithm increments peak current value programmed. And if the load on DCDC is drops below the low threshold, the programmed peak current value is decremented. For a given load on VDDR, after few increments and decrements the final peak current value reaches the optimum setting for the best power efficiency. Each increment or decrement operation can have a delay up to 250 µs, and to reach optimum peak current setting, adaptive peak current control algorithm can take up to 1 ms.
Registers used for Adaptive peak current control: