The ADC status register, STA, contains
two bits – ASCACT and BUSY.
- BUSY equaling ‘1’ indicates that
the ADC is busy performing a sample or conversion operation
- For single channel
single conversion, BUSY signals that a trigger has been received
and sample or conversion is ongoing. BUSY is cleared when the conversion
completes
- For repeat single
conversion, BUSY signals that repeat single operation has begun
and has not ended. BUSY is cleared when ENC is written ‘0’ and the last
conversion completes
- For sequence of
channels conversion, BUSY signals that the sequence of channels
conversion has started. BUSY is cleared at the end of the sequence
- For repeat sequence of
channels conversion, BUSY signals the repeat sequence is
ongoing. BUSY is cleared when ENC is written ‘0’ and the last conversion
in the sequence completes
Note: In case of an ADC start of conversion issued by software through the SC bit,
software has to wait for at least 9 CLKSVT clock cycles if polling for the BUSY
status bit in the program code. This is to account for internal clock
synchronization latencies before the ADC status bit is updated.