SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The AES accelerator consists of the register interface and the finite state machine (FSM).
The register bank provides various options to the user to configure the plaintext source, encryption triggers, µDMA channel triggers, counter size, endianness, alignment, and actions that clear status events and IRQs. In addition to key storage register, there are registers for plaintext and buffer. Users can also configure side effects such as XORing, clearing of events or IRQs, and generation of µDMA and AES triggers. Due to these options, external intervention by the CPU or µDMA is kept to a minimum, thereby significantly increasing throughput.
The FSM operates on the input block, performing the required substitution, shift, and mix operations. A new subkey is generated and XORed with the data each round. Round keys are generated on-the-fly and parallel to data processing. To accommodate CTR cipher mode, the IP offers a 128-bit register acting either as a counter in CTR cipher mode or acting as a pipeline buffer to enable update of next plaintext/ciphertext while AES-128 encryption is ongoing.
Data blocks can be transferred to and from AES either through µDMA or CPU.