SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

20.6 SPI Registers

Table 20-2 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 20-2 should be considered as reserved locations and the register contents should not be modified.

Table 20-2 SPI Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionGo
44hIMASKInterrupt maskGo
48hRISRaw interrupt statusGo
4ChMISMasked interrupt statusGo
50hISETInterrupt setGo
54hICLRInterrupt clearGo
58hIMSETInterrupt mask setGo
5ChIMCLRInterrupt mask clearGo
60hEMUEmulationGo
100hCTL0Control 0Go
104hCTL1Control 1Go
108hCLKCFG0Clock configuration 0Go
10ChCLKCFG1Clock configuration 1Go
110hIFLSInterrupt FIFO Level SelectGo
114hDMACRDMA controlGo
118hRXCRCReceive CRCGo
11ChTXCRCTransmit CRCGo
120hTXFHDR32Header write for 32bitsGo
124hTXFHDR24Header write for 24bitsGo
128hTXFHDR16Header write for 16bitsGo
12ChTXFHDR8Header write for 8bitsGo
130hTXFHDRCAtomic header controlGo
140hRXDATAReceive dataGo
150hTXDATATransmit dataGo
160hSTAStatusGo

Complex bit access types are encoded to fit into small table cells. Table 20-3 shows the codes that are used for access types in this section.

Table 20-3 SPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

20.6.1 DESC Register (Offset = 0h) [Reset = 604D1010h]

DESC is shown in Table 20-4.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 20-4 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR/W604DhModule identifier used to uniquely identify this IP.
15-12STDIPOFFR/W1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR/W0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR/W1hMajor revision of IP (0-15).
3-0MINREVR/W0hMinor revision of IP (0-15).

20.6.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 20-5.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 20-5 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hDMA Done TX event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
7DMARXR/W0hDMA Done RX event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
6IDLER/W0hSPI Idle event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
5TXEMPTYR/W0hTransmit FIFO Empty event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
4TXR/W0hTransmit FIFO event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
3RXR/W0hReceive FIFO event.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2RTOUTR/W0h SPI Receive Time-Out event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1PERR/W0hParity error event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0RXOVFR/W0hRXFIFO overflow event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

20.6.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 20-6.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 20-6 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hDMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.
0h = Interrupt did not occur
1h = Interrupt occurred
7DMARXR/W0hDMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.
0h = Interrupt did not occur
1h = Interrupt occurred
6IDLER/W0hSPI has completed transfers and moved to IDLE mode. This bit is set when STA.BUSY goes low.
0h = Interrupt did not occur
1h = Interrupt occurred
5TXEMPTYR/W0hTransmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.
0h = Interrupt did not occur
1h = Interrupt occurred
4TXR/W0hTransmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur
1h = Interrupt occurred
3RXR/W0hReceive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2RTOUTR/W0hSPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by CTL1.RTOUT value. This is applicable only in peripheral mode.
0h = Interrupt did not occur
1h = Interrupt occurred
1PERR/W0hParity error event. This bit is set if a Parity error has been detected
0h = Interrupt did not occur
1h = Interrupt occurred
0RXOVFR/W0hRXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur
1h = Interrupt occurred

20.6.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 20-7.

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Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 20-7 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hMasked DMA Done event for TX.
0h = Interrupt did not occur
1h = Interrupt occurred
7DMARXR/W0hMasked DMA Done event for RX.
0h = Interrupt did not occur
1h = Interrupt occurred
6IDLER/W0hMasked SPI IDLE event.
0h = Interrupt did not occur
1h = Interrupt occurred
5TXEMPTYR/W0hMasked Transmit FIFO Empty event.
0h = Interrupt did not occur
1h = Interrupt occurred
4TXR/W0hMasked Transmit FIFO event.
0h = Interrupt did not occur
1h = Interrupt occurred
3RXR/W0hMasked receive FIFO event.
0h = Interrupt did not occur
1h = Interrupt occurred
2RTOUTR/W0hMasked SPI Receive Time-Out event.
0h = Interrupt did not occur
1h = Interrupt occurred
1PERR/W0hMasked Parity error event.
0h = Interrupt did not occur
1h = Interrupt occurred
0RXOVFR/W0hMasked RXFIFO overflow event.
0h = Interrupt did not occur
1h = Interrupt occurred

20.6.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 20-8.

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Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 20-8 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hSet DMA Done event for TX.
0h = Writing 0 has no effect
1h = Set Interrupt
7DMARXR/W0hSet DMA Done event for RX.
0h = Writing 0 has no effect
1h = Set Interrupt
6IDLER/W0hSet SPI IDLE event.
0h = Writing 0 has no effect
1h = Set Interrupt
5TXEMPTYR/W0hSet Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Set Interrupt
4TXR/W0hSet Transmit FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
3RXR/W0hSet Receive FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
2RTOUTR/W0hSet SPI Receive Time-Out Event.
0h = Writing 0 has no effect
1h = Set Interrrupt Mask
1PERR/W0hSet Parity error event.
0h = Writing 0 has no effect
1h = Set Interrupt
0RXOVFR/W0hSet RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Set Interrupt

20.6.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 20-9.

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Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 20-9 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hClear DMA Done event for TX.
0h = Writing 0 has no effect
1h = Clear Interrupt
7DMARXR/W0hClear DMA Done event for RX.
0h = Writing 0 has no effect
1h = Clear Interrupt
6IDLER/W0hClear SPI IDLE event.
0h = Writing 0 has no effect
1h = Clear Interrupt
5TXEMPTYR/W0hClear Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Clear Interrupt
4TXR/W0hClear Transmit FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
3RXR/W0hClear Receive FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
2RTOUTR/W0hClear SPI Receive Time-Out Event.
0h = Writing 0 has no effect
1h = Set Interrrupt Mask
1PERR/W0hClear Parity error event.
0h = Writing 0 has no effect
1h = Clear Interrupt
0RXOVFR/W0hClear RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Clear Interrupt

20.6.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 20-10.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 20-10 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hSet DMA Done for TX event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
7DMARXR/W0hSet DMA Done for RX event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
6IDLER/W0hSet SPI IDLE event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
5TXEMPTYR/W0hSet Transmit FIFO Empty event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
4TXR/W0hSet Transmit FIFO event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
3RXR/W0hSet Receive FIFO event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
2RTOUTR/W0hSet SPI Receive Time-Out event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
1PERR/W0hSet Parity error event mask
0h = Writing 0 has no effect
1h = Set interrupt mask
0RXOVFR/W0hSet RXFIFO overflow event mask
0h = Writing 0 has no effect
1h = Set interrupt mask

20.6.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 20-11.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 20-11 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hClear DMA Done for TX event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
7DMARXR/W0hClear DMA Done for RX event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
6IDLER/W0hClear SPI IDLE event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
5TXEMPTYR/W0hClear Transmit FIFO Empty event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
4TXR/W0hClear Transmit FIFO event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
3RXR/W0hClear Receive FIFO event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
2RTOUTR/W0hClear SPI Receive Time-Out event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
1PERR/W0hClear Parity error event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
0RXOVFR/W0hClear RXFIFO overflow event mask
0h = Writing 0 has no effect
1h = Clear interrupt mask

20.6.9 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 20-12.

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Emulation control register. This register controls the behavior of the IP related to core halted input.

Table 20-12 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hHalt control
0h = Free run option. The IP ignores the state of the core halted input.
1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary (end of word boundary, based on DSS configuration) from where it can resume without corruption.

20.6.10 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 20-13.

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SPI control register 0

Table 20-13 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17IDLEPOCIR/W0hThe Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.
0h = POCI output idle value of '0'
1h = POCI outputs idle value of '1'
16GPCRCENR/W0hGeneral purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit must be 0 when SPI is enabled.
0h = Transmit side CRC unit is not available for general purpose software use
1h = Transmit side CRC unit is available for general purpose software use
15CRCPOLYR/W0hCRC polynomial selection.
0h = Selects 8-bit CCITT CRC polynomial
1h = Selects 16-bit CCITT CRC polynomial
14AUTOCRCR/W0hAuto insert CRC
0h = Do not insert CRC into TXFIFO upon TXFIFO underflow
1h = Insert CRC into TXFIFO upon TXFIFO underflow
13CRCENDR/W0hCRC16 Endianness
0h = Auto-insertion of CRC16 is most-significant byte first
1h = Auto-insertion of CRC16 is least-significant byte first
12CSCLRR/W0hClear shift register counter on CS inactive.
This bit is relevant only in the peripheral mode, when CTL1.MS=0.
0h = Disable automatic clear of shift register when CS goes inactive.
1h = Enable automatic clear of shift register when CS goes inactive.
11FIFORSTR/W0hThis bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.
0h = FIFO pointers reset completed when 0 is read
1h = Trigger FIFO pointers reset when written to 1.
10HWCSNR/W0hHardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in -
a. CS is de-asserted
b. All data bytes are transmitted
c. CS is asserted
0h = HWCSN Disable
1h = HWCSN Enable
9SPHR/W0hSCLK phase (Motorola SPI frame format only).
This bit selects the clock edge that captures data and enables it to change state.
It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.
0h = Data is captured on the first clock edge transition.
1h = Data is captured on the second clock edge transition.
8SPOR/W0hSCLK polarity (Motorola SPI frame format only).
0h = SPI produces a steady state LO value on the SCLK
1h = SPI produces a steady state HI value on the SCLK
7RESERVEDR0hReserved
6-5FRFR/W0hFrame format select
0h = Motorola SPI frame format (3-wire mode)
1h = Motorola SPI frame format (4-wire mode)
2h = TI synchronous serial frame format
3h = MICROWIRE frame format
4RESERVEDR0hReserved
3-0DSSR/W0hData size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.
3h = 4-bits data size
4h = 5-bits data size
5h = 6-bits data size
6h = 7-bits data size
7h = 8-bits data size
8h = 9-bits data size
9h = 10-bits data size
Ah = 11-bits data size
Bh = 12-bits data size
Ch = 13-bits data size
Dh = 14-bits data size
Eh = 15-bits data size
Fh = 16-bits data size

20.6.11 CTL1 Register (Offset = 104h) [Reset = 00000004h]

CTL1 is shown in Table 20-14.

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SPI control register 1

Table 20-14 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24RTOUTR/W0hReceive Timeout (only for Peripheral mode)
Defines the number of CLKSVT clock cycles after which the Receive Timeout flag RIS.RTOUT is set.
A value of 0 disables this function.
23-16REPTXR/W0hCounter to repeat last transfer (only in controller mode)
0: repeat last transfer is disabled.
x: repeat the last transfer with the provided value.
The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated REPTX number of times, so the data will be transferred x+1 times in total.
It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
15-12CDMODER/W0hCommnd Data Mode. This bit field value determines the behavior of C/D or CS signal when CDEN = 1. CS pin held low indicates command phase and CS pin held high indicates data phase.
When CDMODE = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode).
When CDMODE = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode).
When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by CDMODE value for the command phase and held high for the remaining transfers in the data phase (automatic mode).
When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation indicates the remaining bytes to be transferred in the command phase.
0h = Manual mode: Data
Fh = Manual mode: Command
11CDENR/W0hCommand/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers (CTL0.DSS = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.
0h = C/D Mode Disable
1h = C/D Mode Enable
10-8RESERVEDR0hReserved
7PBSR/W0hParity bit select
0h = Bit 0 is used for Parity
1h = Bit 1 is used for Parity, Bit 0 is ignored
6PESR/W0hEven parity select.
0h = Odd Parity mode
1h = Even Parity mode
5PENR/W0hParity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits.
In case of parity mismatch the parity error flag RIS.PER will be set. This feature is available only in SPI controller mode.
0h = Disable Parity function
1h = Enable Parity function
4MSBR/W0hMSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.
0h = LSB first
1h = MSB first
3PODR/W0hPeripheral data output disable.
This bit is relevant only in the peripheral mode, MS=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.
0h = SPI can drive the POCI output in peripheral mode.
1h = SPI cannot drive the POCI output in peripheral mode.
2MSR/W1hController or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.EN=0.
0h = Select Peripheral mode
1h = Select Controller mode
1LBMR/W0hLoop back mode control
0h = Disable loopback mode. Normal serial port operation enabled.
1h = Enable loopback mode. Output of transmit serial shifter is connected to input of receive serial shifter internally.
0ENR/W0hSPI enable.
NOTE: This bit field must be set to 1 using a separate write access, after the other bit fields have been configured.
0h = SPI is disabled
1h = SPI Enabled and released for operation.

20.6.12 CLKCFG0 Register (Offset = 108h) [Reset = 00000000h]

CLKCFG0 is shown in Table 20-15.

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Clock configuration register 0. This register is used to configure the clock prescaler.

Table 20-15 CLKCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0PRESCR/W0hPrescaler configuration
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

20.6.13 CLKCFG1 Register (Offset = 10Ch) [Reset = 00000000h]

CLKCFG1 is shown in Table 20-16.

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Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode.

Table 20-16 CLKCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16DSAMPLER/W0hDelayed sampling. In controller mode the data on the POCI pin will be delayed sampled by the defined CLKSVT clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice.
15-10RESERVEDR0hReserved
9-0SCRR/W0hSerial clock divider. This is used to generate the transmit and receive bit rate of the SPI.
The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value can be from 0 to 1023.

20.6.14 IFLS Register (Offset = 110h) [Reset = 00000202h]

IFLS is shown in Table 20-17.

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Interrupt FIFO level select register. This register can be used to define the levels at which the RIS.TX, RIS.RX flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the IFLS.TXSEL and IFLS.RXSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Table 20-17 IFLS Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8RXSELR/W2hReceive FIFO Level Select. The trigger points for the receive interrupt are as follows:
0h = Reserved
1h = RX FIFO >= 1/4 full
2h = RX FIFO >= 1/2 full (default)
3h = RX FIFO >= 3/4 full
4h = Reserved
5h = RX FIFO is full
6h = Reserved
7h = Trigger when RX FIFO contains >= 1 byte
7-3RESERVEDR0hReserved
2-0TXSELR/W2hTransmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:
0h = Reserved
1h = TX FIFO <= 3/4 empty
2h = TX FIFO <= 1/2 empty (default)
3h = TX FIFO <= 1/4 empty
4h = Reserved
5h = TX FIFO is empty
6h = Reserved
7h = Trigger when TX FIFO has >= 1 byte free

20.6.15 DMACR Register (Offset = 114h) [Reset = 00000000h]

DMACR is shown in Table 20-18.

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uDMA Control Register

Table 20-18 DMACR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8TXENR/W0hTransmit DMA enable. If this bit is set to 1, DMA for the trasmit FIFO is enabled.
0h = Disable TX DMA
1h = Enable TX DMA
7-1RESERVEDR0hReserved
0RXENR/W0hReceive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
0h = Disable RX DMA
1h = Enable RX DMA

20.6.16 RXCRC Register (Offset = 118h) [Reset = 00000000h]

RXCRC is shown in Table 20-19.

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Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0.

Table 20-19 RXCRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value
SW should read RXCRC register at the end of data transmission to reinitiaze the seed value to all ones

20.6.17 TXCRC Register (Offset = 11Ch) [Reset = 00000000h]

TXCRC is shown in Table 20-20.

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Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0.

Table 20-20 TXCRC Register Field Descriptions
BitFieldTypeResetDescription
31AUTOCRCINSR0hStatus to indicate if Auto CRC has been inserted into TXFIFO.
This is applicable only if CTL0.AUTOCRC enable bit is set.
SW should read TXCRC register to clear auto inserted CRC at the end of the transfer.
0h = Auto CRC not yet inserted
1h = Auto CRC inserted
30-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value

20.6.18 TXFHDR32 Register (Offset = 120h) [Reset = 00000000h]

TXFHDR32 is shown in Table 20-21.

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Header update reigster for 32 bits of header data into the TXFIFO.

Table 20-21 TXFHDR32 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write four bytes of header data into the TXFIFO

20.6.19 TXFHDR24 Register (Offset = 124h) [Reset = 00000000h]

TXFHDR24 is shown in Table 20-22.

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Header update reigster for 24 bits of header data into the TXFIFO.

Table 20-22 TXFHDR24 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write three bytes of header data into the TXFIFO.

20.6.20 TXFHDR16 Register (Offset = 128h) [Reset = 00000000h]

TXFHDR16 is shown in Table 20-23.

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Header update reigster for 16 bits of data into the TXFIFO.

Table 20-23 TXFHDR16 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write two bytes of header data into the TXFIFO.

20.6.21 TXFHDR8 Register (Offset = 12Ch) [Reset = 00000000h]

TXFHDR8 is shown in Table 20-24.

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Header update reigster for 8 bits of header data into the TXFIFO.

Table 20-24 TXFHDR8 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write one byte of header data into the TXFIFO.

20.6.22 TXFHDRC Register (Offset = 130h) [Reset = 00000000h]

TXFHDRC is shown in Table 20-25.

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Atomic Header Control register

Table 20-25 TXFHDRC Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CSGATER/W0hChip Select Gating control register. If this bit is set, header update register writes are blocked when chip select (CS) is active low, and HDRIGN bit is set.
This bit resets to 0.
0h = The first header update register write is not blocked based on CS active status (low).
If no header update occurred when CS was high (inactive), the first header update is allowed when CS is low (active), and the HDRCMT bit is set. The use case is for the external controller to ensure that the SCLK is not driven during this header update.
If the header is already updated when CS is high and inactive, HDRCMT is set immediately when CS drops to active low state, and header writes when CS is low are ignored even if this UNBLK bit is set.
1h = Header update register writes are blocked when CS is active (low)
2HDRCMTR/W0hHeader Committed field. This bit is set when the HDREN bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
0h = Header update is not committed
1h = Header update is committed
1HDRIGNR/W0hHeader Ignored field. When CSGATE is set to BLK, this bit is set when the last Header update register TXFHDRn is written when CS is low or HDRCMT is already set. When CSGATE is set to UNBLK, this bit is set only when the header update register is written when HDRCMT is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
0h = Header update is not ignored
1h = Header update is ignored
0HDRENR/W0hHeader enable field. When CSGATE is set to BLK, this bit has to be set by software to enable atomic header feature. When CSGATE is set to UNBLK, this field is set automatically whenever a write to header update registers TXFHDRn occurs.
0h = Atomic header update feature disable
1h = Atomic header update feature enable

20.6.23 RXDATA Register (Offset = 140h) [Reset = 00000000h]

RXDATA is shown in Table 20-26.

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RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored.

Table 20-26 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hReceived Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer.
Received data less than 16 bits is automatically right-justified in the receive buffer.

20.6.24 TXDATA Register (Offset = 150h) [Reset = 00000000h]

TXDATA is shown in Table 20-27.

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TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last writen value.

Table 20-27 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hTransmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed.
When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.

20.6.25 STA Register (Offset = 160h) [Reset = 0000000Fh]

STA is shown in Table 20-28.

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Status Register

Table 20-28 STA Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8TXFIFOLVLR0hIndicates how many locations of TXFIFO are currently filled with data
7RESERVEDR0hReserved
6TXDONER/W0hTransmit done. Indicates whether the last bit has left the Shift register after a transmission
0h = Last bit has not yet left the Shift register, and the transmission is ongoing.
1h = Last bit has been shifted out, and the transmission is done
5CSDR/W0hDetection of CS deassertion in the middle of a data frame transmission results in this error being set. This feature is only available in the peripheral mode.
0h = No CS posedge is detected before the entire data frame has been transmitted.
1h = An error is generated when CS posedge (deassertion) is detected before the entire data frame is transmitted.
4BUSYR0hSPI Busy status
0h = SPI is in idle mode.
1h = SPI is currently transmitting and/or recieving data, or transmit FIFO is not empty.
3RNFR1hReceive FIFO not full status.
0h = Receive FIFO is full.
1h = Receive FIFO is not full.
2RFER1hReceive FIFO empty status.
0h = Receive FIFO is not empty.
1h = Receive FIFO is empty.
1TNFR1hTransmit FIFO not full status.
0h = Transmit FIFO is full.
1h = Transmit FIFO is not full.
0TFER1hTransmit FIFO empty status.
0h = Transmit FIFO is not empty.
1h = Transmit FIFO is empty.