SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

15.4 DMA Registers

Table 15-7 lists the memory-mapped registers for the DMA registers. All register offset addresses not listed in Table 15-7 should be considered as reserved locations and the register contents should not be modified.

Table 15-7 DMA Registers
OffsetAcronymRegister NameSection
0hSTATUSStatus Register.Go
4hCFGConfiguration Register.Go
8hCTRLChannel Control Data Base Pointer Register.Go
ChALTCTRLChannel Alternate Control Data Base Pointer Register.Go
10hWAITONREQChannel Wait On Request Status Register.Go
14hSOFTREQChannel Software Request Register.Go
18hSETBURSTChannel Set UseBurst Register.Go
1ChCLEARBURSTChannel Clear UseBurst Register.Go
20hSETREQMASKChannel Set Request Mask Register.Go
24hCLEARREQMASKClear Channel Request Mask Register.Go
28hSETCHANNELENSet Channel Enable Register.Go
2ChCLEARCHANNELENClear Channel Enable Register.Go
30hSETCHNLPRIALTChannel Set Primary-Alternate Register.Go
34hCLEARCHNLPRIALTChannel Clear Primary-Alternate Register.Go
38hSETCHNLPRIORITYSet Channel Priority Register.Go
3ChCLEARCHNLPRIORITYClear Channel Priority Register.Go
4ChERRORError Status and Clear Register.Go
504hREQDONEChannel Request Done Register.Go
520hDONEMASKChannel Request Done Mask Register.Go

Complex bit access types are encoded to fit into small table cells. Table 15-8 shows the codes that are used for access types in this section.

Table 15-8 DMA Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

15.4.1 STATUS Register (Offset = 0h) [Reset = 00070000h]

STATUS is shown in Table 15-9.

Return to the Summary Table.

Status Register.

Table 15-9 STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-28TESTR0h
0x0: Controller does not include the integration test logic
0x1: Controller includes the integration test logic
0x2: Undefined
...
0xF: Undefined
27-21RESERVEDR0hReserved
20-16TOTALCHANNELSR7hRegister value returns number of available uDMA channels minus one. For example a read out value of:
0x00: Show that the controller is configured to use 1 uDMA channel
0x01: Shows that the controller is configured to use 2 uDMA channels
...
0x1F: Shows that the controller is configured to use 32 uDMA channels (32-1=31=0x1F)
15-8RESERVEDR0hReserved
7-4STATER0hCurrent state of the control state machine. State can be one of the following:
0x0: Idle
0x1: Reading channel controller data
0x2: Reading source data end pointer
0x3: Reading destination data end pointer
0x4: Reading source data
0x5: Writing destination data
0x6: Waiting for uDMA request to clear
0x7: Writing channel controller data
0x8: Stalled
0x9: Done
0xA: Peripheral scatter-gather transition
0xB: Undefined
...
0xF: Undefined.
3-1RESERVEDR0hReserved
0MASTERENABLER0hShows the enable status of the controller as configured by CFG.MASTERENABLE:
0h = Controller is disabled
1h = Controller is enabled

15.4.2 CFG Register (Offset = 4h) [Reset = 00000000h]

CFG is shown in Table 15-10.

Return to the Summary Table.

Configuration Register.

Table 15-10 CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0hReserved
7-5PRTOCTRLW0hSets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:
Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.
Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring.
Bit [5] Controls HProt[1] to indicate if a privileged access is occurring.
When bit [n] = 1 then the corresponding HProt bit is high.
When bit [n] = 0 then the corresponding HProt bit is low.
This field controls HProt[3:1] signal for all transactions initiated by uDMA except two transactions below:
- the read from the address indicated by source address pointer
- the write to the address indicated by destination address pointer
HProt[3:1] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor.
4-1RESERVEDW0hReserved
0MASTERENABLEW0hEnables the controller.
0h = Disables the controller
1h = Enables the controller

15.4.3 CTRL Register (Offset = 8h) [Reset = 00000000h]

CTRL is shown in Table 15-11.

Return to the Summary Table.

Channel Control Data Base Pointer Register.

Table 15-11 CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-8BASEPTRR/W0hThis register point to the base address for the primary data structures of each uDMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when uDMA is in usage
7-0RESERVEDR0hReserved

15.4.4 ALTCTRL Register (Offset = Ch) [Reset = 00000080h]

ALTCTRL is shown in Table 15-12.

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Channel Alternate Control Data Base Pointer Register.

Table 15-12 ALTCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-0BASEPTRR80hThis register shows the base address for the alternate data structures and is calculated by module, thus read only

15.4.5 WAITONREQ Register (Offset = 10h) [Reset = 000000FFh]

WAITONREQ is shown in Table 15-13.

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Channel Wait On Request Status Register.

Table 15-13 WAITONREQ Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSTATUSRFFhChannel wait on request status:
Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, this channel may come out of active state even if request is still present.
Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it keeps channel Ch in active state until the requests are deasserted. This handshake is necessary for channels where the requester is in an asynchronous domain or can run at slower clock speed than uDMA

15.4.6 SOFTREQ Register (Offset = 14h) [Reset = 00000000h]

SOFTREQ is shown in Table 15-14.

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Channel Software Request Register.

Table 15-14 SOFTREQ Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hSet the appropriate bit to generate a software uDMA request on the corresponding uDMA channel
Bit [Ch] = 0: Does not create a uDMA request for channel Ch
Bit [Ch] = 1: Creates a uDMA request for channel Ch
Writing to a bit where a uDMA channel is not implemented does not create a uDMA request for that channel

15.4.7 SETBURST Register (Offset = 18h) [Reset = 00000000h]

SETBURST is shown in Table 15-15.

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Channel Set UseBurst Register.

Table 15-15 SETBURST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReturns the useburst status, or disables individual channels from generating single uDMA requests. The value R is the arbitration rate and stored in the controller data structure.
Read as:
Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on channel Ch. The controller performs 2R, or single, bus transfers.
Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. The controller only responds to burst transfer requests and performs 2R transfers.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0.
Bit [Ch] = 1: Disables single transfer requests on channel Ch. The controller performs 2R transfers for burst requests.
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.8 CLEARBURST Register (Offset = 1Ch) [Reset = 00000000h]

CLEARBURST is shown in Table 15-16.

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Channel Clear UseBurst Register.

Table 15-16 CLEARBURST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hSet the appropriate bit to enable single transfer requests.
Write as:
Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer requests.
Bit [Ch] = 1: Enables single transfer requests on channel Ch.
Writing to a bit where a uDMA channel is not implemented has no effect.

15.4.9 SETREQMASK Register (Offset = 20h) [Reset = 00000000h]

SETREQMASK is shown in Table 15-17.

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Channel Set Request Mask Register.

Table 15-17 SETREQMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReturns the burst and single request mask status, or disables the corresponding channel from generating uDMA requests.
Read as:
Bit [Ch] = 0: External requests are enabled for channel Ch.
Bit [Ch] = 1: External requests are disabled for channel Ch.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests.
Bit [Ch] = 1: Disables uDMA burst request channel [Ch] and uDMA single request channel [Ch] input from generating uDMA requests.
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.10 CLEARREQMASK Register (Offset = 24h) [Reset = 00000000h]

CLEARREQMASK is shown in Table 15-18.

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Clear Channel Request Mask Register.

Table 15-18 CLEARREQMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hSet the appropriate bit to enable uDMA request for the channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel Ch from generating requests.
Bit [Ch] = 1: Enables channel [Ch] to generate uDMA requests.
Writing to a bit where a uDMA channel is not implemented has no effect.

15.4.11 SETCHANNELEN Register (Offset = 28h) [Reset = 00000000h]

SETCHANNELEN is shown in Table 15-19.

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Set Channel Enable Register.

Table 15-19 SETCHANNELEN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReturns the enable status of the channels, or enable the corresponding channels.
Read as:
Bit [Ch] = 0: Channel Ch is disabled.
Bit [Ch] = 1: Channel Ch is enabled.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel
Bit [Ch] = 1: Enables channel Ch
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.12 CLEARCHANNELEN Register (Offset = 2Ch) [Reset = 00000000h]

CLEARCHANNELEN is shown in Table 15-20.

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Clear Channel Enable Register.

Table 15-20 CLEARCHANNELEN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hSet the appropriate bit to disable the corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels.
Bit [Ch] = 1: Disables channel Ch
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.13 SETCHNLPRIALT Register (Offset = 30h) [Reset = 00000000h]

SETCHNLPRIALT is shown in Table 15-21.

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Channel Set Primary-Alternate Register.

Table 15-21 SETCHNLPRIALT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReturns the channel control data structure status, or selects the alternate data structure for the corresponding uDMA channel.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the primary data structure.
Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel
Bit [Ch] = 1: Selects the alternate data structure for channel Ch
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.14 CLEARCHNLPRIALT Register (Offset = 34h) [Reset = 00000000h]

CLEARCHNLPRIALT is shown in Table 15-22.

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Channel Clear Primary-Alternate Register.

Table 15-22 CLEARCHNLPRIALT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hClears the appropriate bit to select the primary data structure for the corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate data structure.
Bit [Ch] = 1: Selects the primary data structure for channel Ch.
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.15 SETCHNLPRIORITY Register (Offset = 38h) [Reset = 00000000h]

SETCHNLPRIORITY is shown in Table 15-23.

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Set Channel Priority Register.

Table 15-23 SETCHNLPRIORITY Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReturns the channel priority mask status, or sets the channel priority to high.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the default priority level.
Bit [Ch] = 1: uDMA channel Ch is using a high priority level.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default priority level.
Bit [Ch] = 1: Channel Ch uses the high priority level.
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [Reset = 00000000h]

CLEARCHNLPRIORITY is shown in Table 15-24.

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Clear Channel Priority Register.

Table 15-24 CLEARCHNLPRIORITY Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSW0hClear the appropriate bit to select the default priority level for the specified uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority level.
Bit [Ch] = 1: Channel Ch uses the default priority level.
Writing to a bit where a uDMA channel is not implemented has no effect

15.4.17 ERROR Register (Offset = 4Ch) [Reset = 00000000h]

ERROR is shown in Table 15-25.

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Error Status and Clear Register.

Table 15-25 ERROR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATUSR/W0hReturns the status of bus error flag in uDMA, or clears this bit
Read as:
0: No bus error detected
1: Bus error detected
Write as:
0: No effect, status of bus error flag is unchanged.
1: Clears the bus error flag.

15.4.18 REQDONE Register (Offset = 504h) [Reset = 00000000h]

REQDONE is shown in Table 15-26.

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Channel Request Done Register.

Table 15-26 REQDONE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hReflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1.
Read as:
Bit [Ch] = 0: Request has not completed for channel Ch
Bit [Ch] = 1: Request has completed for the channel Ch
Writing a 1 to individual bits would clear the corresponding bit.
Write as:
Bit [Ch] = 0: No effect.
Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0

15.4.19 DONEMASK Register (Offset = 520h) [Reset = 00000000h]

DONEMASK is shown in Table 15-27.

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Channel Request Done Mask Register.

Table 15-27 DONEMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CHNLSR/W0hControls the propagation of the uDMA done and active state to the assigned peripheral. Specifically used for software channels.
Read as:
Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is blocked from contributing to generation of combined uDMA done signal
Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is not blocked from contributing to generation of combined uDMA done signal
Write as:
Bit [Ch] = 0: Allows uDMA done and active state to propagate to the peripherals.
Note that this disables uDMA done state for channel [Ch] from contributing to generation of combined uDMA done signal
Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the peripherals.
Note that this enables uDMA done for channel [Ch] to contribute to generation of combined uDMA done signal.