SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
SPI includes a feature to reset the TX and RX FIFO pointers to flush FIFOs. This must be triggered when no SPI transactions are in progress. If a FIFO flush is triggered when a transaction is in progress, then a second FIFO flush is needed when no operations are ongoing, before restarting new SPI transfers.
The FIFO flush operation is atomic. When CPU writes into SPI.CTL0[11] FIFORST register bit, the SPI hardware internally ensures that TX and RX FIFO pointers are set to zero, and auto-clears the FIFORST bit after 4 CLKSVT clock cycles. CPU can poll the FIFORST bit to identify when the FIFO pointer reset operation has completed.