The debug subsystem (DEBUGSS)
interfaces the serial wire debug (SWD) two-wire physical interface to multiple debug
functions within the device. Debugging of processor execution and the device state
are supported. The DEBUGSS also provides a mailbox system for communicating with
software through SWD.
Key features provided by the debug
subsystem include:
- Two-wire(SWDIO, SWCLK) debug
interface, compatible with both TI and 3rd party debug probes
- On-chip pull-up/pull-down
resistors for SWDIO and SWCLK, respectively, enabled by default
- Support for disabling SWD
functions to use SWD pins as general purpose input/output pins
- Capability of waking the
device from SHUTDOWN mode upon valid SWD activity
- Debug of the processor
- Run, halt, and step debug
support
- 4 hardware breakpoints
(BPU)
- Software-configurable peripheral
behavior during processor debug
- Ability to free run
select peripherals through debug halt
- Ability to halt select
peripherals on a debug halt
- Ability to request reset
and mode changes to the Power Management Control (PMCTL)
- Debug subsystem mailbox (DSSM)
for passing data and control signals between the SWD interface and boot ROM (as
well as application software)
- Support for various security
features, including software password authenticated debugging