SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The channel filter sets a window within which the input must remain stable, otherwise the transition is not passed to the edge detection logic.
The channel filter counts down from CHFILT.LOAD[15:8] while two consecutive input samples are equal. If two consecutive input samples are unequal the filter counter is re-loaded with LOAD. If the channel filter reaches zero the input is passed to the edge detection logic. The filter delays the input signal by at least LOAD + 1 filter clock cycles.
When writing CTL.MODE to any other value than disabled (0x0) the internal channel filter counter is loaded with the LOAD value. Do not change the CHFILT register while the timer is running and CTL.MODE[2:0] is not disabled (0x0).