SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

12.5 RTC Registers

Table 12-1 lists the memory-mapped registers for the RTC registers. All register offset addresses not listed in Table 12-1 should be considered as reserved locations and the register contents should not be modified.

Table 12-1 RTC Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionGo
4hCTLRTC control RegisterGo
8hARMSETChannel Arming SetGo
ChARMCLRChannel Arming ClearGo
18hTIME8URTC Lower Time SliceGo
1ChTIME524MRTC Upper Time SliceGo
28hCH0CC8UChannel0 compare valueGo
38hCH1CC8UChannel1 capture ValueGo
3ChCH1CFGchannel1 Input ConfigurationGo
44hIMASKInterrupt maskGo
48hRISRaw interrupt statusGo
4ChMISMasked interrupt statusGo
50hISETInterrupt setGo
54hICLRInterrupt clearGo
58hIMSETInterrupt mask setGo
5ChIMCLRInterrupt clearGo
60hEMUEmulationGo

Complex bit access types are encoded to fit into small table cells. Table 12-2 shows the codes that are used for access types in this section.

Table 12-2 RTC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

12.5.1 DESC Register (Offset = 0h) [Reset = 64421010h]

DESC is shown in Table 12-3.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 12-3 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR/W6442hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR/W1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR/W0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR/W1hMajor revision of IP (0-15).
3-0MINREVR/W0hMinor revision of IP (0-15).

12.5.2 CTL Register (Offset = 4h) [Reset = 00000000h]

CTL is shown in Table 12-4.

Return to the Summary Table.

RTC Control register. This register controls resetting the of RTC counter

Table 12-4 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RSTW0hRTC counter reset. Writing 1 to this bit will reset the RTC counter, and cause it to resume counting from 0x0
0h = No effect
1h = Reset the timer.

12.5.3 ARMSET Register (Offset = 8h) [Reset = 00000000h]

ARMSET is shown in Table 12-5.

Return to the Summary Table.

RTC channel mode set register. Read to each bit field of this register provides the current channel mode.
- Read of 1'b0 indicates the channel is unarmed.
- Read of 1'b1 indicates the channel is either in capture or compare mode.
A write to each bitfield of this register the following effect:
- Write of 1'b0 has no effect on channel mode.
- Write of 1'b1 has no effect on the compare channel. While write of 1'b1 for capture channel will arm it in capture mode if it is disabled.

Table 12-5 ARMSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CH1R/W0hArming Channel 1 for capture operation.
0h = No effect on the channel
1h = Enable the Channel 1 for capture operation
0CH0R/W0hNo effect on arming the channel. Read will give the status of the Channel 0.
0h = No effect on the channel
1h = No effect on the compare channel

12.5.4 ARMCLR Register (Offset = Ch) [Reset = 00000000h]

ARMCLR is shown in Table 12-6.

Return to the Summary Table.

RTC channel mode clear register. Read to each bit field of this register provides the current channel mode.
- Read of 1'b0 indicates the channel is unarmed.
- Read of 1'b1 indicates the channel is either in capture or compare mode.
A write to each bitfield of this register the following effect:
- Write of 1'b0 has no effect on channel mode.
- Write of 1'b1 for capture/compare channel will disarm it without triggering event unless a compare/capture event happens in the same cycle.

Table 12-6 ARMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CH1R/W0hDisarming Channel 1
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a capture event happens in the same cycle
0CH0R/W0hDisarming Channel 0
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare event happens in the same cycle

12.5.5 TIME8U Register (Offset = 18h) [Reset = 00000000h]

TIME8U is shown in Table 12-7.

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RTC Time value register. 32-bit unsigned integer representing [34:3] time slice of the real time clock counter. The counter runs on LFCLK. This field has a resolution of 8us, and range of about 9.5 hours.

Table 12-7 TIME8U Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hUnsigned integer representing [34:3]slice of real time counter.

12.5.6 TIME524M Register (Offset = 1Ch) [Reset = 00000000h]

TIME524M is shown in Table 12-8.

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RTC time value register. 32-bit unsigned integer representing [50:19] time slice of the real time clock counter. This field has a resolution of about 0.5s and a range of about 71.4 years.

Table 12-8 TIME524M Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hUnsigned integer representing. [50:19]slice of real time counter.

12.5.7 CH0CC8U Register (Offset = 28h) [Reset = 00000000h]

CH0CC8U is shown in Table 12-9.

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Channel 0 compare value. A write to this register automatically enables the channel to trigger an event when RTC timer reaches the programmed value or if the programmed value is 1 sec in the past.

Table 12-9 CH0CC8U Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hRTC Channel 0 compare value. This value is compared against TIME8U.VAL. A Channel 0 event is generated when TIME8U.VAL value reaches or exceeds this compare value.

12.5.8 CH1CC8U Register (Offset = 38h) [Reset = 00000000h]

CH1CC8U is shown in Table 12-10.

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Channel 1 capture value. This register captures the RTC time slice [34:3] on each selected edge of the capture event when the ARMSET.CH1 = 1.

Table 12-10 CH1CC8U Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20-0VALR0hTIME8U.VAL captured value at the last selected edge of capture event.

12.5.9 CH1CFG Register (Offset = 3Ch) [Reset = 00000000h]

CH1CFG is shown in Table 12-11.

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Channel 1 configuration register. This register can be used to select the capture edge for generating the capture event.

Table 12-11 CH1CFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EDGER/W0hEdge detect configuration for capture source
0h = Rising Edge.
1h = Falling Edge.

12.5.10 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 12-12.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 12-12 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1R/W0hChannel 1 Event Interrupt Mask.
0h = Clear Interrupt Mask
1h = Enable Interrrupt Mask
0EV0R/W0hChannel 0 Event Interrupt Mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask

12.5.11 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 12-13.

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Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 12-13 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1R0hRaw interrupt status for Channel 1 event.
This bit is set to 1 when a capture event is received on Channel 1.
This bit will be cleared when the bit in ICLR.EV1 is set to 1 or when the captured time value is read from the CH1CC8U register.
0h = Interrupt did not occur
1h = Interrupt occured
0EV0R0hRaw interrupt status for Channel 0 event.
This bit is set to 1 when a compare event occurs on Channel 0.
This bit will be cleared. When the corresponding bit in ICLR.EV0 is set to 1. Or when a new compare value is written in CH0CC8U register
0h = Interrupt did not occur
1h = Interrupt occured

12.5.12 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 12-14.

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Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 12-14 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1R0hMasked interrupt status for channel 1 event.
0h = Interrupt did not occur
1h = Interrupt occured
0EV0R0hMasked interrupt status for channel 0 event.
0h = Interrupt did not occur
1h = Interrupt occured

12.5.13 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 12-15.

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Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 12-15 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1W0hSet Channel 1 event Interrupt.
0h = Writing 0 has no effect
1h = Set interrupt
0EV0W0hSet Channel 0 event Interrupt.
0h = Writing 0 has no effect
1h = Set interrupt

12.5.14 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 12-16.

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Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 12-16 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1W0hClears channel 1 event interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
0EV0W0hClears channel 0 event interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt.

12.5.15 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 12-17.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 12-17 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1W0hSet channel 1 event interrupt mask.
0h = Writing 0 has no effect
1h = Set interrupt mask
0EV0W0hSet channel 0 event interrupt mask.
0h = Writing 0 has no effect
1h = Set interrupt mask

12.5.16 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 12-18.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 12-18 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EV1W0hClears Channel 1 event interrupt mask.
0h = Writing 0 has no effect
1h = Clear Interrupt Mask
0EV0W0hClears Channel 0 event interrupt mask.
0h = Writing 0 has no effect
1h = Clear Interrupt Mask

12.5.17 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 12-19.

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Emulation control register. This register controls the behavior of the IP related to core halted input.

Table 12-19 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hHalt control.
0h = Free run option. The IP ignores the state of the core halted input.
1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption.