SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The SPI includes a programmable bit rate clock divider and prescaler to generate the serial output clock.
The serial bit rate is derived by dividing down the input clock, CLKSVT (48MHz).
First, the clock is divided by a division PRESC from 1 to 8, which is programmed in SPI.CLKCFG0 (1 means that the clock is not divided). The clock is further divided by a value from 1 to 1024, which is 1 + SCR, where SCR is the value programmed in SPI.CLKCFG1.
Equation 9 defines the frequency of the output clock SCLK.
The maximum SPI frequency supported with controller and peripheral modes depends on the device clock option and IO option. Please refer to specific device data sheet spec for more information.