SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

21.5 I2C Registers

Table 21-1 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 21-1 should be considered as reserved locations and the register contents should not be modified.

Table 21-1 I2C Registers
OffsetAcronymRegister NameSection
0hTOARTarget Own AddressGo
4hTSTATarget Control and StatusGo
4hTCTLTarget controlGo
8hTDRTarget DataGo
ChTIMRTarget Interrupt MaskGo
10hTRISTarget Raw Interrupt StatusGo
14hTMISTarget Masked Interrupt StatusGo
18hTICRTarget Interrupt ClearGo
800hCTAController Target AddressGo
804hCSTAController Control and StatusGo
804hCCTLController controlGo
808hCDRController DataGo
80ChCTPRController Timer PeriodGo
810hCIMRController Interrupt MaskGo
814hCRISController Raw Interrupt StatusGo
818hCMISController Masked Interrupt StatusGo
81ChCICRController Interrupt ClearGo
820hCCRController ConfigurationGo

Complex bit access types are encoded to fit into small table cells. Table 21-2 shows the codes that are used for access types in this section.

Table 21-2 I2C Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

21.5.1 TOAR Register (Offset = 0h) [Reset = 00000000h]

TOAR is shown in Table 21-3.

Return to the Summary Table.

Target Own Address
This register consists of seven address bits that identify this I2C device on the I2C bus.

Table 21-3 TOAR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6-0OARR/W0hTarget own address. This field specifies bits a6 through a0 of the target address.

21.5.2 TSTA Register (Offset = 4h) [Reset = 00000000h]

TSTA is shown in Table 21-4.

Return to the Summary Table.

Target status
This register functions as a status register of the target.

Table 21-4 TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2FBRR0hFirst byte received.
This bit is only applicable when the TSTA.RREQ bit is set and is automatically cleared when data has been read from the TDR register.
Note: This bit is not used for target transmit operations.
0h = The first byte following the target's own address has not been received
1h = The first byte following the target's own address has been received.
1TREQR0hThis field reflects the transmit request status
0h = No outstanding transmit request
1h = The I2C has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the TDR register
0RREQR0hThis field reflects the receive request status.
0h = No outstanding receive data
1h = The target has outstanding receive data from the external controller and is using clock stretching to delay the controller until data has been read from the TDR register

21.5.3 TCTL Register (Offset = 4h) [Reset = 00000000h]

TCTL is shown in Table 21-5.

Return to the Summary Table.

Target control
This registers functions as a target control register

Table 21-5 TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0DAW0hThis field sets the device active control
0h = Disable the target operation
1h = Enable the target operation

21.5.4 TDR Register (Offset = 8h) [Reset = 00000000h]

TDR is shown in Table 21-6.

Return to the Summary Table.

Target data register
This register contains the data to be transmitted when in the target transmit state, and the data received
when in the target receive state.

Table 21-6 TDR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0DATAR/W0hData for transfer. This field contains the data for transfer during a target receive or a transmit operation. When written, the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write to the controller for transmit or by an external controller to the target for receive.

21.5.5 TIMR Register (Offset = Ch) [Reset = 00000000h]

TIMR is shown in Table 21-7.

Return to the Summary Table.

Target interrupt mask
This register controls whether a raw interrupt is promoted to a controller interrupt

Table 21-7 TIMR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2STOPIMR/W0hStop condition interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask
1STARTIMR/W0hStart condition interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask
0DATAIMR/W0hData interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask

21.5.6 TRIS Register (Offset = 10h) [Reset = 00000000h]

TRIS is shown in Table 21-8.

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Target raw interrupt status
This register shows the unmasked interrupt status.

Table 21-8 TRIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2STOPRISR0hStop condition raw interrupt status
This bit is cleared by writing a 1 to TICR.STOPIC.
0h = Interrupt did not occur
1h = Interrupt occured
1STARTRISR0hStart condition raw interrupt status
This bit is cleared by writing a 1 to TICR.STARTIC.
0h = Interrupt did not occur
1h = Interrupt occured
0DATARISR0hData raw interrupt status
This bit is cleared by writing a 1 to TICR.DATAIC.
0h = Interrupt did not occur
1h = Interrupt occured

21.5.7 TMIS Register (Offset = 14h) [Reset = 00000000h]

TMIS is shown in Table 21-9.

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Target Masked Interrupt Status
This register shows which interrupt is active (based on result from TRIS and TIMR registers).

Table 21-9 TMIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2STOPMISR0hStop condition masked interrupt status
This bit is cleared by writing a 1 to TICR.STOPIC.
0h = Masked interrupt did not occur
1h = Masked interrupt occured
1STARTMISR0hStart condition masked interrupt status
This bit is cleared by writing a 1 to TICR.STARTIC.
0h = Masked interrupt did not occur
1h = Masked interrput occured
0DATAMISR0hStart condition masked interrupt status
This bit is cleared by writing a 1 to TICR.DATAIC.
0h = Masked interrupt did not occur
1h = Masked interrupt occured

21.5.8 TICR Register (Offset = 18h) [Reset = 00000000h]

TICR is shown in Table 21-10.

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Target Interrupt Clear
This register clears the raw interrupt TRIS

Table 21-10 TICR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2STOPICW0hStop condition interrupt clear
0h = No effect
1h = Clear interrupt
Writing 1 to this bit clears TRIS.STOPRIS and TMIS.STOPMIS
1STARTICW0hStart condition interrupt clear
0h = No effect
1h = Clear interrupt
Writing 1 to this bit clears TRIS.STARTRIS and TMIS.STARTMIS
0DATAICW0hData interrupt clear
0h = No effect
1h = Clear interrupt
Writing 1 to this bit clears TRIS.DATARIS and TMIS.DATAMIS

21.5.9 CTA Register (Offset = 800h) [Reset = 00000000h]

CTA is shown in Table 21-11.

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Controller target address
This register contains seven address bits of the target to be accessed by the controller (a6-a0), and an CTA.RS bit determining if the next operation is a receive or transmit

Table 21-11 CTA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-1SAR/W0hController target address
Defines which target is addressed for the transaction in controller mode
0RSR/W0hReceive or Send
This bit-field specifies the next operation with addressed target CTA.SA.
0h = Transmit/send data to target
1h = Receive data from target

21.5.10 CSTA Register (Offset = 804h) [Reset = 00000020h]

CSTA is shown in Table 21-12.

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Controller status
This register functions as a controller status register

Table 21-12 CSTA Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6BUSBSYR0hBus busy
Note:The bit changes based on the CCTRL.START and CCTRL.STOP conditions.
0h = The bus is idle.
1h = The bus is busy.
5IDLER1hThis field specifies whether I2C is idle or not
0h = The controller is not idle.
1h = The controller is idle.
4ARBLSTR0hThe filed specifies the arbitration status
0h = The controller won arbitration.
1h = The controller lost arbitration.
3DATACKNR0hThis field contains Data acknowledge status
0h = The transmitted data was acknowledged
1h = The transmitted data was not acknowledged
2ADRACKNR0hThis field reflects the address acknowledge status
0h = The transmitted address was acknowledged
1h = The transmitted address was not acknowledged
1ERRR0hThis field reflects the error status
0h = No error was detected on the last operation
1h = An error occurred with the last operation
0BUSYR0hThis field reflects the I2C busy status
Note: The I2C controller requires four CLKSVT clock cycles to assert the BUSY status after I2C controller operation has been initiated through a write into CCTL register.
Hence after programming CCTL register, application is requested to wait for four CLKSVT clock cycles before issuing a controller status inquiry through a read from CSTA register. Any prior inquiry would result in wrong status being reported.
0h = The controller is idle
1h = The controller is busy

21.5.11 CCTL Register (Offset = 804h) [Reset = 00000000h]

CCTL is shown in Table 21-13.

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Controller control
This register functions as a controller control register

Table 21-13 CCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3ACKW0hThis field is to enable the data acknowledge.
Note:This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the target transmitter.
0h = The received data byte is not acknowledged automatically by the controller
1h = The received data byte is acknowledged automatically by the controller
2STOPW0hThis field is to set stop condition .
Note: This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition.
0h = The controller does not generate the stop condition
1h = The controller generates the stop condition
1STARTW0hThis field is to set start or repeated start condition.
0h = The controller does not generate the start condition
1h = The controller generates the start condition.
0RUNW0hThis field is to set the controller enable.
0h = The controller is disabled.
1h = The controller is enabled to transmit or receive data

21.5.12 CDR Register (Offset = 808h) [Reset = 00000000h]

CDR is shown in Table 21-14.

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Controller data
This register contains the data to be transmitted when in the controller transmit state and the data received when in the controller receive state.

Table 21-14 CDR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0DATAR/W0hWhen Read: Last RX Data is returned
When Written: Data is transferred during TX transaction

21.5.13 CTPR Register (Offset = 80Ch) [Reset = 00000001h]

CTPR is shown in Table 21-15.

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Controller timer period
This register specifies the period of the SCL clock.

Table 21-15 CTPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7TPR_7R/W0hMust be set to 0 to set CTPR.TPR. If set to 1, a write to CTPR.TPR will be ignored.
6-0TPRR/W1hSCL clock period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD, where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the timer period register value (range of 1 to 127)
SCL_LP is the SCL low period (fixed at 6).
SCL_HP is the SCL high period (fixed at 4).
CLK_PRD is the CLKSVT period in ns.

21.5.14 CIMR Register (Offset = 810h) [Reset = 00000000h]

CIMR is shown in Table 21-16.

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Controller interrupt mask
This register controls whether a raw interrupt is promoted to a controller interrupt.

Table 21-16 CIMR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0IMR/W0hInterrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask

21.5.15 CRIS Register (Offset = 814h) [Reset = 00000000h]

CRIS is shown in Table 21-17.

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Controller raw interrupt status
This register shows the unmasked interrupt status.

Table 21-17 CRIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0RISR0hRaw interrupt status
This bit is cleared by writing 1 to CICR.IC bit.
0h = Interrupt did not occur
1h = Interrupt occured

21.5.16 CMIS Register (Offset = 818h) [Reset = 00000000h]

CMIS is shown in Table 21-18.

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Controller masked interrupt status
This register shows which interrupt is active (based on result from CRIS and CIMR registers).

Table 21-18 CMIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0MISR0hMasked interrupt status
This bit is cleared by writing 1 to CICR.IC bit.
0h = Masked interrupt did not occur
1h = Masked interrupt occured

21.5.17 CICR Register (Offset = 81Ch) [Reset = 00000000h]

CICR is shown in Table 21-19.

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Controller interrupt clear
This register clears the raw and masked interrupt.

Table 21-19 CICR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0ICW0hInterrupt clear
0h = No effect
1h = Clear Interrupt
Writing 1 to this bit clears CRIS.RIS and CMIS.MIS.

21.5.18 CCR Register (Offset = 820h) [Reset = 00000000h]

CCR is shown in Table 21-20.

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Controller Configuration
This register configures the mode (Controller or Target) and sets the interface for test mode loopback.

Table 21-20 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5TFER/W0hI2C target function enable

0h = Target mode disabled
1h = Target mode enabled
4CFER/W0hI2C controller function enable
0h = Controller mode disabled
1h = Controller mode enabled
3-1RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
0LPBKR/W0hI2C loopback
0h = Test mode (Loopback operation) disabled
1h = Test mode (Loopback operation) enabled