SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

18.10 GPIO Registers

Table 18-38 lists the memory-mapped registers for the GPIO registers. All register offset addresses not listed in Table 18-38 should be considered as reserved locations and the register contents should not be modified.

Table 18-38 GPIO Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionGo
4hDESCEXModule Description ExtendedGo
44hIMASKInterrupt MaskGo
4ChRISRaw interrupt statusGo
54hMISMasked interrupt statusGo
5ChISETInterrupt setGo
64hICLRInterrupt clearGo
6ChIMSETInterrupt mask setGo
74hIMCLRInterrupt mask clearGo
100hDOUT3_0Alias for Data out 3 to 0Go
104hDOUT7_4Alias for Data out 7 to 4Go
108hDOUT11_8Alias for Data out 11 to 8Go
10ChDOUT15_12Alias for Data out 15 to 12Go
110hDOUT19_16Alias for Data out 19 to 16Go
114hDOUT23_20Alias for Data out 23 to 20Go
118hDOUT27_24Alias for Data out 27 to 24Go
200hDOUT31_0Data out 31 to 0Go
210hDOUTSET31_0Data out set 31 to 0Go
220hDOUTCLR31_0Data out clear 31 to 0Go
230hDOUTTGL31_0Data out toggle 31 to 0Go
300hDOUTTGL3_0Alias for Data out toggle 3 to 0Go
304hDOUTTGL7_4Alias for Data out toggle 7 to 4Go
308hDOUTTGL11_8Alias for Data out toggle 11 to 8Go
30ChDOUTTGL15_12Alias for Data out toggle 15 to 12Go
310hDOUTTGL19_16Alias for Data out toggle 19 to 16Go
314hDOUTTGL23_20Alias for Data out toggle 23 to 20Go
318hDOUTTGL27_24Alias for Data out toggle 27 to 24Go
400hDOE3_0Alias for Data out enable 3 to 0Go
404hDOE7_4Alias for Data out enable 7 to 4Go
408hDOE11_8Alias for Data out enable 11 to 8Go
40ChDOE15_12Alias for Data out enable 15 to 12Go
410hDOE19_16Alias for Data out enable 19 to 16Go
414hDOE23_20Alias for Data out enable 23 to 20Go
418hDOE27_24Alias for Data out enable 27 to 24Go
500hDOE31_0Data out enable 31 to 0Go
510hDOESET31_0Data out enable set 31 to 0Go
520hDOECLR31_0Data out enable clear 31 to 0Go
530hDOETGL31_0Data out enable toggle 31 to 0Go
600hDIN3_0Alias for Data input 3 to 0Go
604hDIN7_4Alias for Data input 7 to 4Go
608hDIN11_8Alias for Data input 11 to 8Go
60ChDIN15_12Alias for Data input 15 to 12Go
610hDIN19_16Alias for Data input 19 to 16Go
614hDIN23_20Alias for Data input 23 to 20Go
618hDIN27_24Alias for Data input 27 to 24Go
700hDIN31_0Data input 31 to 0Go
800hEVTCFGEvent configurationGo

Complex bit access types are encoded to fit into small table cells. Table 18-39 shows the codes that are used for access types in this section.

Table 18-39 GPIO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

18.10.1 DESC Register (Offset = 0h) [Reset = 7C491010h]

DESC is shown in Table 18-40.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 18-40 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR7C49hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

18.10.2 DESCEX Register (Offset = 4h) [Reset = 00000019h]

DESCEX is shown in Table 18-41.

Return to the Summary Table.

Extended Description Register. This register provides configuration details of the IP to software drivers and end users.

Table 18-41 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0NUMDIOR19hThis provides the total number of DIOs supported by GPIO. The number of DIOs supprted is NUMDIO + 1

18.10.3 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 18-42.

Return to the Summary Table.

Interrupt mask for DIO pins

Table 18-42 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R/W0hInterrupt mask for DIO25
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
24DIO24R/W0hInterrupt mask for DIO24
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
23DIO23R/W0hInterrupt mask for DIO23
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
22DIO22R/W0hInterrupt mask for DIO22
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
21DIO21R/W0hInterrupt mask for DIO21
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
20DIO20R/W0hInterrupt mask for DIO20
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
19DIO19R/W0hInterrupt mask for DIO19
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
18DIO18R/W0hInterrupt mask for DIO18
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
17DIO17R/W0hInterrupt mask for DIO17
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
16DIO16R/W0hInterrupt mask for DIO16
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
15DIO15R/W0hInterrupt mask for DIO15
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
14DIO14R/W0hInterrupt mask for DIO14
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
13DIO13R/W0hInterrupt mask for DIO13
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
12DIO12R/W0hInterrupt mask for DIO12
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
11DIO11R/W0hInterrupt mask for DIO11
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
10DIO10R/W0hInterrupt mask for DIO10
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
9DIO9R/W0hInterrupt mask for DIO9
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
8DIO8R/W0hInterrupt mask for DIO8
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
7DIO7R/W0hInterrupt mask for DIO7
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
6DIO6R/W0hInterrupt mask for DIO6
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
5DIO5R/W0hInterrupt mask for DIO5
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
4DIO4R/W0hInterrupt mask for DIO4
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
3DIO3R/W0hInterrupt mask for DIO3
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2DIO2R/W0hInterrupt mask for DIO2
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1DIO1R/W0hInterrupt mask for DIO1
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0DIO0R/W0hInterrupt mask for DIO0
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

18.10.4 RIS Register (Offset = 4Ch) [Reset = 00000000h]

RIS is shown in Table 18-43.

Return to the Summary Table.

Raw interrupt flag for DIO pins

Table 18-43 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R0hRaw interrupt flag for DIO25
0h = Interrupt did not occur
1h = Interrupt occured
24DIO24R0hRaw interrupt flag for DIO24
0h = Interrupt did not occur
1h = Interrupt occured
23DIO23R0hRaw interrupt flag for DIO23
0h = Interrupt did not occur
1h = Interrupt occured
22DIO22R0hRaw interrupt flag for DIO22
0h = Interrupt did not occur
1h = Interrupt occured
21DIO21R0hRaw interrupt flag for DIO21
0h = Interrupt did not occur
1h = Interrupt occured
20DIO20R0hRaw interrupt flag for DIO20
0h = Interrupt did not occur
1h = Interrupt occured
19DIO19R0hRaw interrupt flag for DIO19
0h = Interrupt did not occur
1h = Interrupt occured
18DIO18R0hRaw interrupt flag for DIO18
0h = Interrupt did not occur
1h = Interrupt occured
17DIO17R0hRaw interrupt flag for DIO17
0h = Interrupt did not occur
1h = Interrupt occured
16DIO16R0hRaw interrupt flag for DIO16
0h = Interrupt did not occur
1h = Interrupt occured
15DIO15R0hRaw interrupt flag for DIO15
0h = Interrupt did not occur
1h = Interrupt occured
14DIO14R0hRaw interrupt flag for DIO14
0h = Interrupt did not occur
1h = Interrupt occured
13DIO13R0hRaw interrupt flag for DIO13
0h = Interrupt did not occur
1h = Interrupt occured
12DIO12R0hRaw interrupt flag for DIO12
0h = Interrupt did not occur
1h = Interrupt occured
11DIO11R0hRaw interrupt flag for DIO11
0h = Interrupt did not occur
1h = Interrupt occured
10DIO10R0hRaw interrupt flag for DIO10
0h = Interrupt did not occur
1h = Interrupt occured
9DIO9R0hRaw interrupt flag for DIO9
0h = Interrupt did not occur
1h = Interrupt occured
8DIO8R0hRaw interrupt flag for DIO8
0h = Interrupt did not occur
1h = Interrupt occured
7DIO7R0hRaw interrupt flag for DIO7
0h = Interrupt did not occur
1h = Interrupt occured
6DIO6R0hRaw interrupt flag for DIO6
0h = Interrupt did not occur
1h = Interrupt occured
5DIO5R0hRaw interrupt flag for DIO5
0h = Interrupt did not occur
1h = Interrupt occured
4DIO4R0hRaw interrupt flag for DIO4
0h = Interrupt did not occur
1h = Interrupt occured
3DIO3R0hRaw interrupt flag for DIO3
0h = Interrupt did not occur
1h = Interrupt occured
2DIO2R0hRaw interrupt flag for DIO2
0h = Interrupt did not occur
1h = Interrupt occured
1DIO1R0hRaw interrupt flag for DIO1
0h = Interrupt did not occur
1h = Interrupt occured
0DIO0R0hRaw interrupt flag for DIO0
0h = Interrupt did not occur
1h = Interrupt occured

18.10.5 MIS Register (Offset = 54h) [Reset = 00000000h]

MIS is shown in Table 18-44.

Return to the Summary Table.

Masked interrupt flag for DIO pins

Table 18-44 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R0hMasked interrupt flag for DIO25
0h = Interrupt did not occur
1h = Interrupt occured
24DIO24R0hMasked interrupt flag for DIO24
0h = Interrupt did not occur
1h = Interrupt occured
23DIO23R0hMasked interrupt flag for DIO23
0h = Interrupt did not occur
1h = Interrupt occured
22DIO22R0hMasked interrupt flag for DIO22
0h = Interrupt did not occur
1h = Interrupt occured
21DIO21R0hMasked interrupt flag for DIO21
0h = Interrupt did not occur
1h = Interrupt occured
20DIO20R0hMasked interrupt flag for DIO20
0h = Interrupt did not occur
1h = Interrupt occured
19DIO19R0hMasked interrupt flag for DIO19
0h = Interrupt did not occur
1h = Interrupt occured
18DIO18R0hMasked interrupt flag for DIO18
0h = Interrupt did not occur
1h = Interrupt occured
17DIO17R0hMasked interrupt flag for DIO17
0h = Interrupt did not occur
1h = Interrupt occured
16DIO16R0hMasked interrupt flag for DIO16
0h = Interrupt did not occur
1h = Interrupt occured
15DIO15R0hMasked interrupt flag for DIO15
0h = Interrupt did not occur
1h = Interrupt occured
14DIO14R0hMasked interrupt flag for DIO14
0h = Interrupt did not occur
1h = Interrupt occured
13DIO13R0hMasked interrupt flag for DIO13
0h = Interrupt did not occur
1h = Interrupt occured
12DIO12R0hMasked interrupt flag for DIO12
0h = Interrupt did not occur
1h = Interrupt occured
11DIO11R0hMasked interrupt flag for DIO11
0h = Interrupt did not occur
1h = Interrupt occured
10DIO10R0hMasked interrupt flag for DIO10
0h = Interrupt did not occur
1h = Interrupt occured
9DIO9R0hMasked interrupt flag for DIO9
0h = Interrupt did not occur
1h = Interrupt occured
8DIO8R0hMasked interrupt flag for DIO8
0h = Interrupt did not occur
1h = Interrupt occured
7DIO7R0hMasked interrupt flag for DIO7
0h = Interrupt did not occur
1h = Interrupt occured
6DIO6R0hMasked interrupt flag for DIO6
0h = Interrupt did not occur
1h = Interrupt occured
5DIO5R0hMasked interrupt flag for DIO5
0h = Interrupt did not occur
1h = Interrupt occured
4DIO4R0hMasked interrupt flag for DIO4
0h = Interrupt did not occur
1h = Interrupt occured
3DIO3R0hMasked interrupt flag for DIO3
0h = Interrupt did not occur
1h = Interrupt occured
2DIO2R0hMasked interrupt flag for DIO2
0h = Interrupt did not occur
1h = Interrupt occured
1DIO1R0hMasked interrupt flag for DIO1
0h = Interrupt did not occur
1h = Interrupt occured
0DIO0R0hMasked interrupt flag for DIO0
0h = Interrupt did not occur
1h = Interrupt occured

18.10.6 ISET Register (Offset = 5Ch) [Reset = 00000000h]

ISET is shown in Table 18-45.

Return to the Summary Table.

Set interrupt flag in RIS by writing a one

Table 18-45 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hSet DIO25 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
24DIO24W0hSet DIO24 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
23DIO23W0hSet DIO23 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
22DIO22W0hSet DIO22 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
21DIO21W0hSet DIO21 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
20DIO20W0hSet DIO20 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
19DIO19W0hSet DIO19 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
18DIO18W0hSet DIO18 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
17DIO17W0hSet DIO17 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
16DIO16W0hSet DIO16 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
15DIO15W0hSet DIO15 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
14DIO14W0hSet DIO14 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
13DIO13W0hSet DIO13 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
12DIO12W0hSet DIO12 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
11DIO11W0hSet DIO11 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
10DIO10W0hSet DIO10 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
9DIO9W0hSet DIO9 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
8DIO8W0hSet DIO8 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
7DIO7W0hSet DIO7 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
6DIO6W0hSet DIO6 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
5DIO5W0hSet DIO5 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
4DIO4W0hSet DIO4 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
3DIO3W0hSet DIO3 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
2DIO2W0hSet DIO2 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
1DIO1W0hSet DIO1 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt
0DIO0W0hSet DIO0 in RIS
0h = Writing 0 has no effect
1h = Set Interrupt

18.10.7 ICLR Register (Offset = 64h) [Reset = 00000000h]

ICLR is shown in Table 18-46.

Return to the Summary Table.

Clear interrupt flag in RIS by writing a one

Table 18-46 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hClears DIO25 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
24DIO24W0hClears DIO24 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
23DIO23W0hClears DIO23 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
22DIO22W0hClears DIO22 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
21DIO21W0hClears DIO21 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
20DIO20W0hClears DIO20 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
19DIO19W0hClears DIO19 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
18DIO18W0hClears DIO18 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
17DIO17W0hClears DIO17 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
16DIO16W0hClears DIO16 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
15DIO15W0hClears DIO15 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
14DIO14W0hClears DIO14 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
13DIO13W0hClears DIO13 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
12DIO12W0hClears DIO12 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
11DIO11W0hClears DIO11 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
10DIO10W0hClears DIO10 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
9DIO9W0hClears DIO9 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
8DIO8W0hClears DIO8 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
7DIO7W0hClears DIO7 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
6DIO6W0hClears DIO6 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
5DIO5W0hClears DIO5 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
4DIO4W0hClears DIO4 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
3DIO3W0hClears DIO3 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
2DIO2W0hClears DIO2 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
1DIO1W0hClears DIO1 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt
0DIO0W0hClears DIO0 in RIS
0h = Writing 0 has no effect
1h = Clear Interrupt

18.10.8 IMSET Register (Offset = 6Ch) [Reset = 00000000h]

IMSET is shown in Table 18-47.

Return to the Summary Table.

Set interrupt mask in IMASK by writing a one

Table 18-47 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hSets DIO25 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
24DIO24W0hSets DIO24 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
23DIO23W0hSets DIO23 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
22DIO22W0hSets DIO22 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
21DIO21W0hSets DIO21 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
20DIO20W0hSets DIO20 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
19DIO19W0hSets DIO19 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
18DIO18W0hSets DIO18 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
17DIO17W0hSets DIO17 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
16DIO16W0hSets DIO16 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
15DIO15W0hSets DIO15 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
14DIO14W0hSets DIO14 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
13DIO13W0hSets DIO13 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
12DIO12W0hSets DIO12 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
11DIO11W0hSets DIO11 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
10DIO10W0hSets DIO10 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
9DIO9W0hSets DIO9 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
8DIO8W0hSets DIO8 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
7DIO7W0hSets DIO7 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
6DIO6W0hSets DIO6 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
5DIO5W0hSets DIO5 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
4DIO4W0hSets DIO4 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
3DIO3W0hSets DIO3 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
2DIO2W0hSets DIO2 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
1DIO1W0hSets DIO1 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask
0DIO0W0hSets DIO0 in IMASK
0h = Writing 0 has no effect
1h = Set interrupt mask

18.10.9 IMCLR Register (Offset = 74h) [Reset = 00000000h]

IMCLR is shown in Table 18-48.

Return to the Summary Table.

Clear interrupt mask in IMASK by writing a one

Table 18-48 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hClears DIO25 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
24DIO24W0hClears DIO24 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
23DIO23W0hClears DIO23 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
22DIO22W0hClears DIO22 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
21DIO21W0hClears DIO21 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
20DIO20W0hClears DIO20 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
19DIO19W0hClears DIO19 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
18DIO18W0hClears DIO18 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
17DIO17W0hClears DIO17 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
16DIO16W0hClears DIO16 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
15DIO15W0hClears DIO15 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
14DIO14W0hClears DIO14 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
13DIO13W0hClears DIO13 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
12DIO12W0hClears DIO12 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
11DIO11W0hClears DIO11 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
10DIO10W0hClears DIO10 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
9DIO9W0hClears DIO9 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
8DIO8W0hClears DIO8 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
7DIO7W0hClears DIO7 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
6DIO6W0hClears DIO6 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
5DIO5W0hClears DIO5 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
4DIO4W0hClears DIO4 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
3DIO3W0hClears DIO3 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
2DIO2W0hClears DIO2 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
1DIO1W0hClears DIO1 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask
0DIO0W0hClears DIO0 in IMASK
0h = Writing 0 has no effect
1h = Clear interrupt mask

18.10.10 DOUT3_0 Register (Offset = 100h) [Reset = 00000000h]

DOUT3_0 is shown in Table 18-49.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[3:0] bits.

Table 18-49 DOUT3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R/W0hData output for DIO3
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO2R/W0hData output for DIO2
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO1R/W0hData output for DIO1
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO0R/W0hData output for DIO0
0h = Output is set to 0
1h = Output is set to 1

18.10.11 DOUT7_4 Register (Offset = 104h) [Reset = 00000000h]

DOUT7_4 is shown in Table 18-50.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[7:4] bits

Table 18-50 DOUT7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R/W0hData output for DIO7
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO6R/W0hData output for DIO6
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO5R/W0hData output for DIO5
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO4R/W0hData output for DIO4
0h = Output is set to 0
1h = Output is set to 1

18.10.12 DOUT11_8 Register (Offset = 108h) [Reset = 00000000h]

DOUT11_8 is shown in Table 18-51.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[11:8] bits

Table 18-51 DOUT11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R/W0hData output for DIO11
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO10R/W0hData output for DIO10
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO9R/W0hData output for DIO9
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO8R/W0hData output for DIO8
0h = Output is set to 0
1h = Output is set to 1

18.10.13 DOUT15_12 Register (Offset = 10Ch) [Reset = 00000000h]

DOUT15_12 is shown in Table 18-52.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[15:12] bits

Table 18-52 DOUT15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R/W0hData output for DIO15
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO14R/W0hData output for DIO14
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO13R/W0hData output for DIO13
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO12R/W0hData output for DIO12
0h = Output is set to 0
1h = Output is set to 1

18.10.14 DOUT19_16 Register (Offset = 110h) [Reset = 00000000h]

DOUT19_16 is shown in Table 18-53.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[19:16] bits

Table 18-53 DOUT19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R/W0hData output for DIO19
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO18R/W0hData output for DIO18
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO17R/W0hData output for DIO17
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO16R/W0hData output for DIO16
0h = Output is set to 0
1h = Output is set to 1

18.10.15 DOUT23_20 Register (Offset = 114h) [Reset = 00000000h]

DOUT23_20 is shown in Table 18-54.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[23:20] bits

Table 18-54 DOUT23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R/W0hData output for DIO23
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0hReserved
16DIO22R/W0hData output for DIO22
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0hReserved
8DIO21R/W0hData output for DIO21
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO20R/W0hData output for DIO20
0h = Output is set to 0
1h = Output is set to 1

18.10.16 DOUT27_24 Register (Offset = 118h) [Reset = 00000000h]

DOUT27_24 is shown in Table 18-55.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[27:24] bits

Table 18-55 DOUT27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DIO25R/W0hData output for DIO25
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0hReserved
0DIO24R/W0hData output for DIO24
0h = Output is set to 0
1h = Output is set to 1

18.10.17 DOUT31_0 Register (Offset = 200h) [Reset = 00000000h]

DOUT31_0 is shown in Table 18-56.

Return to the Summary Table.

Data Output for DIO 31 to 0 pins.

Table 18-56 DOUT31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R/W0hData output for DIO25
0h = Output is set to 0
1h = Output is set to 1
24DIO24R/W0hData output for DIO24
0h = Output is set to 0
1h = Output is set to 1
23DIO23R/W0hData output for DIO23
0h = Output is set to 0
1h = Output is set to 1
22DIO22R/W0hData output for DIO22
0h = Output is set to 0
1h = Output is set to 1
21DIO21R/W0hData output for DIO21
0h = Output is set to 0
1h = Output is set to 1
20DIO20R/W0hData output for DIO20
0h = Output is set to 0
1h = Output is set to 1
19DIO19R/W0hData output for DIO19
0h = Output is set to 0
1h = Output is set to 1
18DIO18R/W0hData output for DIO18
0h = Output is set to 0
1h = Output is set to 1
17DIO17R/W0hData output for DIO17
0h = Output is set to 0
1h = Output is set to 1
16DIO16R/W0hData output for DIO16
0h = Output is set to 0
1h = Output is set to 1
15DIO15R/W0hData output for DIO15
0h = Output is set to 0
1h = Output is set to 1
14DIO14R/W0hData output for DIO14
0h = Output is set to 0
1h = Output is set to 1
13DIO13R/W0hData output for DIO13
0h = Output is set to 0
1h = Output is set to 1
12DIO12R/W0hData output for DIO12
0h = Output is set to 0
1h = Output is set to 1
11DIO11R/W0hData output for DIO11
0h = Output is set to 0
1h = Output is set to 1
10DIO10R/W0hData output for DIO10
0h = Output is set to 0
1h = Output is set to 1
9DIO9R/W0hData output for DIO9
0h = Output is set to 0
1h = Output is set to 1
8DIO8R/W0hData output for DIO8
0h = Output is set to 0
1h = Output is set to 1
7DIO7R/W0hData output for DIO7
0h = Output is set to 0
1h = Output is set to 1
6DIO6R/W0hData output for DIO6
0h = Output is set to 0
1h = Output is set to 1
5DIO5R/W0hData output for DIO5
0h = Output is set to 0
1h = Output is set to 1
4DIO4R/W0hData output for DIO4
0h = Output is set to 0
1h = Output is set to 1
3DIO3R/W0hData output for DIO3
0h = Output is set to 0
1h = Output is set to 1
2DIO2R/W0hData output for DIO2
0h = Output is set to 0
1h = Output is set to 1
1DIO1R/W0hData output for DIO1
0h = Output is set to 0
1h = Output is set to 1
0DIO0R/W0hData output for DIO0
0h = Output is set to 0
1h = Output is set to 1

18.10.18 DOUTSET31_0 Register (Offset = 210h) [Reset = 00000000h]

DOUTSET31_0 is shown in Table 18-57.

Return to the Summary Table.

Alias regiser to set the corresponding bits of DOUT31_0 register.

Table 18-57 DOUTSET31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hSet bit DOUT31_0.DIO25
0h = No effect
1h = Set
24DIO24W0hSet bit DOUT31_0.DIO24
0h = No effect
1h = Set
23DIO23W0hSet bit DOUT31_0.DIO23
0h = No effect
1h = Set
22DIO22W0hSet bit DOUT31_0.DIO22
0h = No effect
1h = Set
21DIO21W0hSet bit DOUT31_0.DIO21
0h = No effect
1h = Set
20DIO20W0hSet bit DOUT31_0.DIO20
0h = No effect
1h = Set
19DIO19W0hSet bit DOUT31_0.DIO19
0h = No effect
1h = Set
18DIO18W0hSet bit DOUT31_0.DIO18
0h = No effect
1h = Set
17DIO17W0hSet bit DOUT31_0.DIO17
0h = No effect
1h = Set
16DIO16W0hSet bit DOUT31_0.DIO16
0h = No effect
1h = Set
15DIO15W0hSet bit DOUT31_0.DIO15
0h = No effect
1h = Set
14DIO14W0hSet bit DOUT31_0.DIO14
0h = No effect
1h = Set
13DIO13W0hSet bit DOUT31_0.DIO13
0h = No effect
1h = Set
12DIO12W0hSet bit DOUT31_0.DIO12
0h = No effect
1h = Set
11DIO11W0hSet bit DOUT31_0.DIO11
0h = No effect
1h = Set
10DIO10W0hSet bit DOUT31_0.DIO10
0h = No effect
1h = Set
9DIO9W0hSet bit DOUT31_0.DIO9
0h = No effect
1h = Set
8DIO8W0hSet bit DOUT31_0.DIO8
0h = No effect
1h = Set
7DIO7W0hSet bit DOUT31_0.DIO7
0h = No effect
1h = Set
6DIO6W0hSet bit DOUT31_0.DIO6
0h = No effect
1h = Set
5DIO5W0hSet bit DOUT31_0.DIO5
0h = No effect
1h = Set
4DIO4W0hSet bit DOUT31_0.DIO4
0h = No effect
1h = Set
3DIO3W0hSet bit DOUT31_0.DIO3
0h = No effect
1h = Set
2DIO2W0hSet bit DOUT31_0.DIO2
0h = No effect
1h = Set
1DIO1W0hSet bit DOUT31_0.DIO1
0h = No effect
1h = Set
0DIO0W0hSet bit DOUT31_0.DIO0
0h = No effect
1h = Set

18.10.19 DOUTCLR31_0 Register (Offset = 220h) [Reset = 00000000h]

DOUTCLR31_0 is shown in Table 18-58.

Return to the Summary Table.

Alias regiser to clear the corresponding bits of DOUT31_0 register.

Table 18-58 DOUTCLR31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hClear bit DOUT31_0.DIO25
0h = No effect
1h = Clear
24DIO24W0hClear bit DOUT31_0.DIO24
0h = No effect
1h = Clear
23DIO23W0hClear bit DOUT31_0.DIO23
0h = No effect
1h = Clear
22DIO22W0hClear bit DOUT31_0.DIO22
0h = No effect
1h = Clear
21DIO21W0hClear bit DOUT31_0.DIO21
0h = No effect
1h = Clear
20DIO20W0hClear bit DOUT31_0.DIO20
0h = No effect
1h = Clear
19DIO19W0hClear bit DOUT31_0.DIO19
0h = No effect
1h = Clear
18DIO18W0hClear bit DOUT31_0.DIO18
0h = No effect
1h = Clear
17DIO17W0hClear bit DOUT31_0.DIO17
0h = No effect
1h = Clear
16DIO16W0hClear bit DOUT31_0.DIO16
0h = No effect
1h = Clear
15DIO15W0hClear bit DOUT31_0.DIO15
0h = No effect
1h = Clear
14DIO14W0hClear bit DOUT31_0.DIO14
0h = No effect
1h = Clear
13DIO13W0hClear bit DOUT31_0.DIO13
0h = No effect
1h = Clear
12DIO12W0hClear bit DOUT31_0.DIO12
0h = No effect
1h = Clear
11DIO11W0hClear bit DOUT31_0.DIO11
0h = No effect
1h = Clear
10DIO10W0hClear bit DOUT31_0.DIO10
0h = No effect
1h = Clear
9DIO9W0hClear bit DOUT31_0.DIO9
0h = No effect
1h = Clear
8DIO8W0hClear bit DOUT31_0.DIO8
0h = No effect
1h = Clear
7DIO7W0hClear bit DOUT31_0.DIO7
0h = No effect
1h = Clear
6DIO6W0hClear bit DOUT31_0.DIO6
0h = No effect
1h = Clear
5DIO5W0hClear bit DOUT31_0.DIO5
0h = No effect
1h = Clear
4DIO4W0hClear bit DOUT31_0.DIO4
0h = No effect
1h = Clear
3DIO3W0hClear bit DOUT31_0.DIO3
0h = No effect
1h = Clear
2DIO2W0hClear bit DOUT31_0.DIO2
0h = No effect
1h = Clear
1DIO1W0hClear bit DOUT31_0.DIO1
0h = No effect
1h = Clear
0DIO0W0hClear bit DOUT31_0.DIO0
0h = No effect
1h = Clear

18.10.20 DOUTTGL31_0 Register (Offset = 230h) [Reset = 00000000h]

DOUTTGL31_0 is shown in Table 18-59.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0 register.

Table 18-59 DOUTTGL31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hToggles bit DOUT31_0.DIO25
0h = No effect
1h = Toggle
24DIO24W0hToggles bit DOUT31_0.DIO24
0h = No effect
1h = Toggle
23DIO23W0hToggles bit DOUT31_0.DIO23
0h = No effect
1h = Toggle
22DIO22W0hToggles bit DOUT31_0.DIO22
0h = No effect
1h = Toggle
21DIO21W0hToggles bit DOUT31_0.DIO21
0h = No effect
1h = Toggle
20DIO20W0hToggles bit DOUT31_0.DIO20
0h = No effect
1h = Toggle
19DIO19W0hToggles bit DOUT31_0.DIO19
0h = No effect
1h = Toggle
18DIO18W0hToggles bit DOUT31_0.DIO18
0h = No effect
1h = Toggle
17DIO17W0hToggles bit DOUT31_0.DIO17
0h = No effect
1h = Toggle
16DIO16W0hToggles bit DOUT31_0.DIO16
0h = No effect
1h = Toggle
15DIO15W0hToggles bit DOUT31_0.DIO15
0h = No effect
1h = Toggle
14DIO14W0hToggles bit DOUT31_0.DIO14
0h = No effect
1h = Toggle
13DIO13W0hToggles bit DOUT31_0.DIO13
0h = No effect
1h = Toggle
12DIO12W0hToggles bit DOUT31_0.DIO12
0h = No effect
1h = Toggle
11DIO11W0hToggles bit DOUT31_0.DIO11
0h = No effect
1h = Toggle
10DIO10W0hToggles bit DOUT31_0.DIO10
0h = No effect
1h = Toggle
9DIO9W0hToggles bit DOUT31_0.DIO9
0h = No effect
1h = Toggle
8DIO8W0hToggles bit DOUT31_0.DIO8
0h = No effect
1h = Toggle
7DIO7W0hToggles bit DOUT31_0.DIO7
0h = No effect
1h = Toggle
6DIO6W0hToggles bit DOUT31_0.DIO6
0h = No effect
1h = Toggle
5DIO5W0hToggles bit DOUT31_0.DIO5
0h = No effect
1h = Toggle
4DIO4W0hToggles bit DOUT31_0.DIO4
0h = No effect
1h = Toggle
3DIO3W0hToggles bit DOUT31_0.DIO3
0h = No effect
1h = Toggle
2DIO2W0hToggles bit DOUT31_0.DIO2
0h = No effect
1h = Toggle
1DIO1W0hToggles bit DOUT31_0.DIO1
0h = No effect
1h = Toggle
0DIO0W0hToggles bit DOUT31_0.DIO0
0h = No effect
1h = Toggle

18.10.21 DOUTTGL3_0 Register (Offset = 300h) [Reset = 00000000h]

DOUTTGL3_0 is shown in Table 18-60.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[3:0] register.

Table 18-60 DOUTTGL3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3W0hToggles bit DOUT31_0.DIO3
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO2W0hToggles bit DOUT31_0.DIO2
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO1W0hToggles bit DOUT31_0.DIO1
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO0W0hToggles bit DOUT31_0.DIO0
0h = No effect
1h = Toggle

18.10.22 DOUTTGL7_4 Register (Offset = 304h) [Reset = 00000000h]

DOUTTGL7_4 is shown in Table 18-61.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[7:4] register.

Table 18-61 DOUTTGL7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7W0hToggles bit DOUT31_0.DIO7
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO6W0hToggles bit DOUT31_0.DIO6
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO5W0hToggles bit DOUT31_0.DIO5
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO4W0hToggles bit DOUT31_0.DIO4
0h = No effect
1h = Toggle

18.10.23 DOUTTGL11_8 Register (Offset = 308h) [Reset = 00000000h]

DOUTTGL11_8 is shown in Table 18-62.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[11:8] register.

Table 18-62 DOUTTGL11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11W0hToggles bit DOUT31_0.DIO11
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO10W0hToggles bit DOUT31_0.DIO10
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO9W0hToggles bit DOUT31_0.DIO9
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO8W0hToggles bit DOUT31_0.DIO8
0h = No effect
1h = Toggle

18.10.24 DOUTTGL15_12 Register (Offset = 30Ch) [Reset = 00000000h]

DOUTTGL15_12 is shown in Table 18-63.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[15:12] register.

Table 18-63 DOUTTGL15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15W0hToggles bit DOUT31_0.DIO15
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO14W0hToggles bit DOUT31_0.DIO14
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO13W0hToggles bit DOUT31_0.DIO13
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO12W0hToggles bit DOUT31_0.DIO12
0h = No effect
1h = Toggle

18.10.25 DOUTTGL19_16 Register (Offset = 310h) [Reset = 00000000h]

DOUTTGL19_16 is shown in Table 18-64.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[19:16] register.

Table 18-64 DOUTTGL19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19W0hToggles bit DOUT31_0.DIO19
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO18W0hToggles bit DOUT31_0.DIO18
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO17W0hToggles bit DOUT31_0.DIO17
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO16W0hToggles bit DOUT31_0.DIO16
0h = No effect
1h = Toggle

18.10.26 DOUTTGL23_20 Register (Offset = 314h) [Reset = 00000000h]

DOUTTGL23_20 is shown in Table 18-65.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[23:20] register.

Table 18-65 DOUTTGL23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23W0hToggles bit DOUT31_0.DIO23
0h = No effect
1h = Toggle
23-17RESERVEDR0hReserved
16DIO22W0hToggles bit DOUT31_0.DIO22
0h = No effect
1h = Toggle
15-9RESERVEDR0hReserved
8DIO21W0hToggles bit DOUT31_0.DIO21
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO20W0hToggles bit DOUT31_0.DIO20
0h = No effect
1h = Toggle

18.10.27 DOUTTGL27_24 Register (Offset = 318h) [Reset = 00000000h]

DOUTTGL27_24 is shown in Table 18-66.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOUT31_0[27:24] register.

Table 18-66 DOUTTGL27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DIO25W0hToggles bit DOUT31_0.DIO25
0h = No effect
1h = Toggle
7-1RESERVEDR0hReserved
0DIO24W0hToggles bit DOUT31_0.DIO24
0h = No effect
1h = Toggle

18.10.28 DOE3_0 Register (Offset = 400h) [Reset = 00000000h]

DOE3_0 is shown in Table 18-67.

Return to the Summary Table.

Alias register for byte access to DOE31_0[3:0] bits.

Table 18-67 DOE3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R/W0hData output enable for DIO3
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO2R/W0hData output enable for DIO2
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO1R/W0hData output enable for DIO1
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO0R/W0hData output enable for DIO0
0h = Output disabled
1h = Output enabled

18.10.29 DOE7_4 Register (Offset = 404h) [Reset = 00000000h]

DOE7_4 is shown in Table 18-68.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[7:4] bits.

Table 18-68 DOE7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R/W0hData output enable for DIO7
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO6R/W0hData output enable for DIO6
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO5R/W0hData output enable for DIO5
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO4R/W0hData output enable for DIO4
0h = Output disabled
1h = Output enabled

18.10.30 DOE11_8 Register (Offset = 408h) [Reset = 00000000h]

DOE11_8 is shown in Table 18-69.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[11:8] bits.

Table 18-69 DOE11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R/W0hData output enable for DIO11
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO10R/W0hData output enable for DIO10
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO9R/W0hData output enable for DIO9
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO8R/W0hData output enable for DIO8
0h = Output disabled
1h = Output enabled

18.10.31 DOE15_12 Register (Offset = 40Ch) [Reset = 00000000h]

DOE15_12 is shown in Table 18-70.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[15:12] bits.

Table 18-70 DOE15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R/W0hData output enable for DIO15
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO14R/W0hData output enable for DIO14
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO13R/W0hData output enable for DIO13
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO12R/W0hData output enable for DIO12
0h = Output disabled
1h = Output enabled

18.10.32 DOE19_16 Register (Offset = 410h) [Reset = 00000000h]

DOE19_16 is shown in Table 18-71.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[19:16] bits.

Table 18-71 DOE19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R/W0hData output enable for DIO19
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO18R/W0hData output enable for DIO18
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO17R/W0hData output enable for DIO17
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO16R/W0hData output enable for DIO16
0h = Output disabled
1h = Output enabled

18.10.33 DOE23_20 Register (Offset = 414h) [Reset = 00000000h]

DOE23_20 is shown in Table 18-72.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[23:20] bits.

Table 18-72 DOE23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R/W0hData output enable for DIO23
0h = Output disabled
1h = Output enabled
23-17RESERVEDR0hReserved
16DIO22R/W0hData output enable for DIO22
0h = Output disabled
1h = Output enabled
15-9RESERVEDR0hReserved
8DIO21R/W0hData output enable for DIO21
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO20R/W0hData output enable for DIO20
0h = Output disabled
1h = Output enabled

18.10.34 DOE27_24 Register (Offset = 418h) [Reset = 00000000h]

DOE27_24 is shown in Table 18-73.

Return to the Summary Table.

Alias register for byte access to DOUT31_0[27:24] bits.

Table 18-73 DOE27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DIO25R/W0hData output enable for DIO25
0h = Output disabled
1h = Output enabled
7-1RESERVEDR0hReserved
0DIO24R/W0hData output enable for DIO24
0h = Output disabled
1h = Output enabled

18.10.35 DOE31_0 Register (Offset = 500h) [Reset = 00000000h]

DOE31_0 is shown in Table 18-74.

Return to the Summary Table.

Data output control for DIO 31 to 0 pins.

Table 18-74 DOE31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R/W0hData output enable for DIO25
0h = Output disabled
1h = Output enabled
24DIO24R/W0hData output enable for DIO24
0h = Output disabled
1h = Output enabled
23DIO23R/W0hData output enable for DIO23
0h = Output disabled
1h = Output enabled
22DIO22R/W0hData output enable for DIO22
0h = Output disabled
1h = Output enabled
21DIO21R/W0hData output enable for DIO21
0h = Output disabled
1h = Output enabled
20DIO20R/W0hData output enable for DIO20
0h = Output disabled
1h = Output enabled
19DIO19R/W0hData output enable for DIO19
0h = Output disabled
1h = Output enabled
18DIO18R/W0hData output enable for DIO18
0h = Output disabled
1h = Output enabled
17DIO17R/W0hData output enable for DIO17
0h = Output disabled
1h = Output enabled
16DIO16R/W0hData output enable for DIO16
0h = Output disabled
1h = Output enabled
15DIO15R/W0hData output enable for DIO15
0h = Output disabled
1h = Output enabled
14DIO14R/W0hData output enable for DIO14
0h = Output disabled
1h = Output enabled
13DIO13R/W0hData output enable for DIO13
0h = Output disabled
1h = Output enabled
12DIO12R/W0hData output enable for DIO12
0h = Output disabled
1h = Output enabled
11DIO11R/W0hData output enable for DIO11
0h = Output disabled
1h = Output enabled
10DIO10R/W0hData output enable for DIO10
0h = Output disabled
1h = Output enabled
9DIO9R/W0hData output enable for DIO9
0h = Output disabled
1h = Output enabled
8DIO8R/W0hData output enable for DIO8
0h = Output disabled
1h = Output enabled
7DIO7R/W0hData output enable for DIO7
0h = Output disabled
1h = Output enabled
6DIO6R/W0hData output enable for DIO6
0h = Output disabled
1h = Output enabled
5DIO5R/W0hData output enable for DIO5
0h = Output disabled
1h = Output enabled
4DIO4R/W0hData output enable for DIO4
0h = Output disabled
1h = Output enabled
3DIO3R/W0hData output enable for DIO3
0h = Output disabled
1h = Output enabled
2DIO2R/W0hData output enable for DIO2
0h = Output disabled
1h = Output enabled
1DIO1R/W0hData output enable for DIO1
0h = Output disabled
1h = Output enabled
0DIO0R/W0hData output enable for DIO0
0h = Output disabled
1h = Output enabled

18.10.36 DOESET31_0 Register (Offset = 510h) [Reset = 00000000h]

DOESET31_0 is shown in Table 18-75.

Return to the Summary Table.

Alias regiser to set the corresponding bits of DOE31_0 register.

Table 18-75 DOESET31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hSets bit DOE31_0.DIO25
0h = No effect
1h = Set
24DIO24W0hSets bit DOE31_0.DIO24
0h = No effect
1h = Set
23DIO23W0hSets bit DOE31_0.DIO23
0h = No effect
1h = Set
22DIO22W0hSets bit DOE31_0.DIO22
0h = No effect
1h = Set
21DIO21W0hSets bit DOE31_0.DIO21
0h = No effect
1h = Set
20DIO20W0hSets bit DOE31_0.DIO20
0h = No effect
1h = Set
19DIO19W0hSets bit DOE31_0.DIO19
0h = No effect
1h = Set
18DIO18W0hSets bit DOE31_0.DIO18
0h = No effect
1h = Set
17DIO17W0hSets bit DOE31_0.DIO17
0h = No effect
1h = Set
16DIO16W0hSets bit DOE31_0.DIO16
0h = No effect
1h = Set
15DIO15W0hSets bit DOE31_0.DIO15
0h = No effect
1h = Set
14DIO14W0hSets bit DOE31_0.DIO14
0h = No effect
1h = Set
13DIO13W0hSets bit DOE31_0.DIO13
0h = No effect
1h = Set
12DIO12W0hSets bit DOE31_0.DIO12
0h = No effect
1h = Set
11DIO11W0hSets bit DOE31_0.DIO11
0h = No effect
1h = Set
10DIO10W0hSets bit DOE31_0.DIO10
0h = No effect
1h = Set
9DIO9W0hSets bit DOE31_0.DIO9
0h = No effect
1h = Set
8DIO8W0hSets bit DOE31_0.DIO8
0h = No effect
1h = Set
7DIO7W0hSets bit DOE31_0.DIO7
0h = No effect
1h = Set
6DIO6W0hSets bit DOE31_0.DIO6
0h = No effect
1h = Set
5DIO5W0hSets bit DOE31_0.DIO5
0h = No effect
1h = Set
4DIO4W0hSets bit DOE31_0.DIO4
0h = No effect
1h = Set
3DIO3W0hSets bit DOE31_0.DIO3
0h = No effect
1h = Set
2DIO2W0hSets bit DOE31_0.DIO2
0h = No effect
1h = Set
1DIO1W0hSets bit DOE31_0.DIO1
0h = No effect
1h = Set
0DIO0W0hSets bit DOE31_0.DIO0
0h = No effect
1h = Set

18.10.37 DOECLR31_0 Register (Offset = 520h) [Reset = 00000000h]

DOECLR31_0 is shown in Table 18-76.

Return to the Summary Table.

Alias regiser to clear the corresponding bits of DOE31_0 register.

Table 18-76 DOECLR31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hClears bit DOE31_0.DIO25
0h = No effect
1h = Clear
24DIO24W0hClears bit DOE31_0.DIO24
0h = No effect
1h = Clear
23DIO23W0hClears bit DOE31_0.DIO23
0h = No effect
1h = Clear
22DIO22W0hClears bit DOE31_0.DIO22
0h = No effect
1h = Clear
21DIO21W0hClears bit DOE31_0.DIO21
0h = No effect
1h = Clear
20DIO20W0hClears bit DOE31_0.DIO20
0h = No effect
1h = Clear
19DIO19W0hClears bit DOE31_0.DIO19
0h = No effect
1h = Clear
18DIO18W0hClears bit DOE31_0.DIO18
0h = No effect
1h = Clear
17DIO17W0hClears bit DOE31_0.DIO17
0h = No effect
1h = Clear
16DIO16W0hClears bit DOE31_0.DIO16
0h = No effect
1h = Clear
15DIO15W0hClears bit DOE31_0.DIO15
0h = No effect
1h = Clear
14DIO14W0hClears bit DOE31_0.DIO14
0h = No effect
1h = Clear
13DIO13W0hClears bit DOE31_0.DIO13
0h = No effect
1h = Clear
12DIO12W0hClears bit DOE31_0.DIO12
0h = No effect
1h = Clear
11DIO11W0hClears bit DOE31_0.DIO11
0h = No effect
1h = Clear
10DIO10W0hClears bit DOE31_0.DIO10
0h = No effect
1h = Clear
9DIO9W0hClears bit DOE31_0.DIO9
0h = No effect
1h = Clear
8DIO8W0hClears bit DOE31_0.DIO8
0h = No effect
1h = Clear
7DIO7W0hClears bit DOE31_0.DIO7
0h = No effect
1h = Clear
6DIO6W0hClears bit DOE31_0.DIO6
0h = No effect
1h = Clear
5DIO5W0hClears bit DOE31_0.DIO5
0h = No effect
1h = Clear
4DIO4W0hClears bit DOE31_0.DIO4
0h = No effect
1h = Clear
3DIO3W0hClears bit DOE31_0.DIO3
0h = No effect
1h = Clear
2DIO2W0hClears bit DOE31_0.DIO2
0h = No effect
1h = Clear
1DIO1W0hClears bit DOE31_0.DIO1
0h = No effect
1h = Clear
0DIO0W0hClears bit DOE31_0.DIO0
0h = No effect
1h = Clear

18.10.38 DOETGL31_0 Register (Offset = 530h) [Reset = 00000000h]

DOETGL31_0 is shown in Table 18-77.

Return to the Summary Table.

Alias regiser to toggle the corresponding bits of DOE31_0 register.

Table 18-77 DOETGL31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25W0hToggles bit DOE31_0.DIO25
0h = No effect
1h = Toggle
24DIO24W0hToggles bit DOE31_0.DIO24
0h = No effect
1h = Toggle
23DIO23W0hToggles bit DOE31_0.DIO23
0h = No effect
1h = Toggle
22DIO22W0hToggles bit DOE31_0.DIO22
0h = No effect
1h = Toggle
21DIO21W0hToggles bit DOE31_0.DIO21
0h = No effect
1h = Toggle
20DIO20W0hToggles bit DOE31_0.DIO20
0h = No effect
1h = Toggle
19DIO19W0hToggles bit DOE31_0.DIO19
0h = No effect
1h = Toggle
18DIO18W0hToggles bit DOE31_0.DIO18
0h = No effect
1h = Toggle
17DIO17W0hToggles bit DOE31_0.DIO17
0h = No effect
1h = Toggle
16DIO16W0hToggles bit DOE31_0.DIO16
0h = No effect
1h = Toggle
15DIO15W0hToggles bit DOE31_0.DIO15
0h = No effect
1h = Toggle
14DIO14W0hToggles bit DOE31_0.DIO14
0h = No effect
1h = Toggle
13DIO13W0hToggles bit DOE31_0.DIO13
0h = No effect
1h = Toggle
12DIO12W0hToggles bit DOE31_0.DIO12
0h = No effect
1h = Toggle
11DIO11W0hToggles bit DOE31_0.DIO11
0h = No effect
1h = Toggle
10DIO10W0hToggles bit DOE31_0.DIO10
0h = No effect
1h = Toggle
9DIO9W0hToggles bit DOE31_0.DIO9
0h = No effect
1h = Toggle
8DIO8W0hToggles bit DOE31_0.DIO8
0h = No effect
1h = Toggle
7DIO7W0hToggles bit DOE31_0.DIO7
0h = No effect
1h = Toggle
6DIO6W0hToggles bit DOE31_0.DIO6
0h = No effect
1h = Toggle
5DIO5W0hToggles bit DOE31_0.DIO5
0h = No effect
1h = Toggle
4DIO4W0hToggles bit DOE31_0.DIO4
0h = No effect
1h = Toggle
3DIO3W0hToggles bit DOE31_0.DIO3
0h = No effect
1h = Toggle
2DIO2W0hToggles bit DOE31_0.DIO2
0h = No effect
1h = Toggle
1DIO1W0hToggles bit DOE31_0.DIO1
0h = No effect
1h = Toggle
0DIO0W0hToggles bit DOE31_0.DIO0
0h = No effect
1h = Toggle

18.10.39 DIN3_0 Register (Offset = 600h) [Reset = 00000000h]

DIN3_0 is shown in Table 18-78.

Return to the Summary Table.

Alias register for byte access to DIN31_0[3:0] bits.

Table 18-78 DIN3_0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO3R0hData input from DIO3
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO2R0hData input from DIO2
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO1R0hData input from DIO1
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO0R0hData input from DIO0
0h = Input value is 0
1h = Input value is 1

18.10.40 DIN7_4 Register (Offset = 604h) [Reset = 00000000h]

DIN7_4 is shown in Table 18-79.

Return to the Summary Table.

Alias register for byte access to DIN31_0[7:4] bits.

Table 18-79 DIN7_4 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO7R0hData input from DIO7
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO6R0hData input from DIO6
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO5R0hData input from DIO5
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO4R0hData input from DIO4
0h = Input value is 0
1h = Input value is 1

18.10.41 DIN11_8 Register (Offset = 608h) [Reset = 00000000h]

DIN11_8 is shown in Table 18-80.

Return to the Summary Table.

Alias register for byte access to DIN31_0[11:8] bits.

Table 18-80 DIN11_8 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO11R0hData input from DIO11
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO10R0hData input from DIO10
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO9R0hData input from DIO9
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO8R0hData input from DIO8
0h = Input value is 0
1h = Input value is 1

18.10.42 DIN15_12 Register (Offset = 60Ch) [Reset = 00000000h]

DIN15_12 is shown in Table 18-81.

Return to the Summary Table.

Alias register for byte access to DIN31_0[15:12] bits.

Table 18-81 DIN15_12 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO15R0hData input from DIO15
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO14R0hData input from DIO14
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO13R0hData input from DIO13
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO12R0hData input from DIO12
0h = Input value is 0
1h = Input value is 1

18.10.43 DIN19_16 Register (Offset = 610h) [Reset = 00000000h]

DIN19_16 is shown in Table 18-82.

Return to the Summary Table.

Alias register for byte access to DIN31_0[19:16] bits.

Table 18-82 DIN19_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO19R0hData input from DIO19
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO18R0hData input from DIO18
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO17R0hData input from DIO17
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO16R0hData input from DIO16
0h = Input value is 0
1h = Input value is 1

18.10.44 DIN23_20 Register (Offset = 614h) [Reset = 00000000h]

DIN23_20 is shown in Table 18-83.

Return to the Summary Table.

Alias register for byte access to DIN31_0[23:20] bits.

Table 18-83 DIN23_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24DIO23R0hData input from DIO23
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0hReserved
16DIO22R0hData input from DIO22
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0hReserved
8DIO21R0hData input from DIO21
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO20R0hData input from DIO20
0h = Input value is 0
1h = Input value is 1

18.10.45 DIN27_24 Register (Offset = 618h) [Reset = 00000000h]

DIN27_24 is shown in Table 18-84.

Return to the Summary Table.

Alias register for byte access to DIN31_0[27:24] bits.

Table 18-84 DIN27_24 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DIO25R0hData input from DIO25
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0hReserved
0DIO24R0hData input from DIO24
0h = Input value is 0
1h = Input value is 1

18.10.46 DIN31_0 Register (Offset = 700h) [Reset = 00000000h]

DIN31_0 is shown in Table 18-85.

Return to the Summary Table.

Data input from DIO 31 to 0 pins.

Table 18-85 DIN31_0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25DIO25R0hData input from DIO25
0h = Input value is 0
1h = Input value is 1
24DIO24R0hData input from DIO24
0h = Input value is 0
1h = Input value is 1
23DIO23R0hData input from DIO23
0h = Input value is 0
1h = Input value is 1
22DIO22R0hData input from DIO22
0h = Input value is 0
1h = Input value is 1
21DIO21R0hData input from DIO21
0h = Input value is 0
1h = Input value is 1
20DIO20R0hData input from DIO20
0h = Input value is 0
1h = Input value is 1
19DIO19R0hData input from DIO19
0h = Input value is 0
1h = Input value is 1
18DIO18R0hData input from DIO18
0h = Input value is 0
1h = Input value is 1
17DIO17R0hData input from DIO17
0h = Input value is 0
1h = Input value is 1
16DIO16R0hData input from DIO16
0h = Input value is 0
1h = Input value is 1
15DIO15R0hData input from DIO15
0h = Input value is 0
1h = Input value is 1
14DIO14R0hData input from DIO14
0h = Input value is 0
1h = Input value is 1
13DIO13R0hData input from DIO13
0h = Input value is 0
1h = Input value is 1
12DIO12R0hData input from DIO12
0h = Input value is 0
1h = Input value is 1
11DIO11R0hData input from DIO11
0h = Input value is 0
1h = Input value is 1
10DIO10R0hData input from DIO10
0h = Input value is 0
1h = Input value is 1
9DIO9R0hData input from DIO9
0h = Input value is 0
1h = Input value is 1
8DIO8R0hData input from DIO8
0h = Input value is 0
1h = Input value is 1
7DIO7R0hData input from DIO7
0h = Input value is 0
1h = Input value is 1
6DIO6R0hData input from DIO6
0h = Input value is 0
1h = Input value is 1
5DIO5R0hData input from DIO5
0h = Input value is 0
1h = Input value is 1
4DIO4R0hData input from DIO4
0h = Input value is 0
1h = Input value is 1
3DIO3R0hData input from DIO3
0h = Input value is 0
1h = Input value is 1
2DIO2R0hData input from DIO2
0h = Input value is 0
1h = Input value is 1
1DIO1R0hData input from DIO1
0h = Input value is 0
1h = Input value is 1
0DIO0R0hData input from DIO0
0h = Input value is 0
1h = Input value is 1

18.10.47 EVTCFG Register (Offset = 800h) [Reset = 00000000h]

EVTCFG is shown in Table 18-86.

Return to the Summary Table.

Event configuration. This register is used to select DIO for GPIO to publish event on SVT event fabric (EVTSVT). It also contains enable bit that is used to mask the event.

Table 18-86 EVTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8EVTENR/W0hEnables GPIO to publish edge qualified selected DIO event on SVT event fabric.
Design note: The edge detector flop is cleared automatically for the selected DIO once the event is published.
0h = Disable
1h = Enable
7-6RESERVEDR0hReserved
5-0DIOSELR/W0hThis is used to select DIO for event generation. For example, DIOSEL = 0x0 selects DIO0 and DIOSEL = 0x8 selects DIO8.
0h = Minimum value
3Fh = Maximum value