SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

10.6 LGPT1 Registers

Table 10-48 lists the memory-mapped registers for the LGPT1 registers. All register offset addresses not listed in Table 10-48 should be considered as reserved locations and the register contents should not be modified.

Table 10-48 LGPT1 Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Go
4hDESCEXDescription ExtendedGo
8hSTARTCFGStart ConfigurationGo
ChCTLTimer ControlGo
10hOUTCTLOutput ControlGo
14hCNTRCounterGo
18hPRECFGClock Prescaler ConfigurationGo
1ChPREEVENTPrescaler EventGo
20hCHFILTChannel Input FilterGo
24hFAULTFaultGo
28hPARKParkGo
2ChDBDLYDead Band DelayGo
30hDBCTLDead Band ControlGo
3ChDMADirect Memory AccsessGo
40hDMARWDirect Memory AccessGo
44hADCTRGADC TriggerGo
48hIOCTLIO ControllerGo
68hIMASKInterrupt mask.Go
6ChRISRaw interrupt status.Go
70hMISMasked interrupt status.Go
74hISETInterrupt set register.Go
78hICLRInterrupt clear register.Go
7ChIMSETInterrupt mask set register.Go
80hIMCLRInterrupt mask clear register.Go
84hEMUDebug controlGo
C0hC0CFGChannel 0 ConfigurationGo
C4hC1CFGChannel 1 ConfigurationGo
C8hC2CFGChannel 2 ConfigurationGo
FChPTGTPipeline TargetGo
100hPC0CCPipeline Channel 0 Capture CompareGo
104hPC1CCPipeline Channel 1 Capture CompareGo
108hPC2CCPipeline Channel 2 Capture CompareGo
13ChTGTTargetGo
140hC0CCChannel 0 Capture CompareGo
144hC1CCChannel 1 Capture CompareGo
148hC2CCChannel 2 Capture CompareGo
17ChPTGTNCPipeline Target No ClearGo
180hPC0CCNCPipeline Channel 0 Capture Compare No ClearGo
184hPC1CCNCPipeline Channel 1 Capture Compare No ClearGo
188hPC2CCNCPipeline Channel 2 Capture Compare No ClearGo
1BChTGTNCTarget No ClearGo
1C0hC0CCNCChannel 0 Capture Compare No ClearGo
1C4hC1CCNCChannel 1 Capture Compare No ClearGo
1C8hC2CCNCChannel 2 Capture Compare No ClearGo

Complex bit access types are encoded to fit into small table cells. Table 10-49 shows the codes that are used for access types in this section.

Table 10-49 LGPT1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

10.6.1 DESC Register (Offset = 0h) [Reset = DE491010h]

DESC is shown in Table 10-50.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 10-50 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDRDE49hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number.
7-4MAJREVR1hMajor revision of IP.
3-0MINREVR0hMinor revision of IP.

10.6.2 DESCEX Register (Offset = 4h) [Reset = 000618C3h]

DESCEX is shown in Table 10-51.

Return to the Summary Table.

Description Extended
This register describes the parameters of the LGPT.

Table 10-51 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19HIRR0hHas IR logic.
18HDBFR1hHas Dead-Band, Fault, and Park logic.
17-14PREWR8hPrescale width. The prescaler can maximum be configured to 2PREW-1.
13HQDECR0hHas Quadrature Decoder.
12HCIFR1hHas channel input filter.
11-8CIFSR8hChannel input filter size. The prevailing state filter can maximum be configured to 2CIFS-1.
7HDMAR1hHas uDMA output and logic.
6HINTR1hHas interrupt output and logic.
5-4CNTRWR0hCounter bit-width.
The maximum counter value is equal to 2CNTRW-1.
0h = 16-bit counter.
1h = 24-bit counter.
2h = 32-bit counter.
3h = RESERVED
3-0NCHR3hNumber of channels.

10.6.3 STARTCFG Register (Offset = 8h) [Reset = 00000000h]

STARTCFG is shown in Table 10-52.

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Start Configuration
This register is only for when CTL.MODE is configured to one of the SYNC modes.
This register defines when this LGPT starts.

Table 10-52 STARTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0LGPT0R/W0hLGPT start

10.6.4 CTL Register (Offset = Ch) [Reset = 00000000h]

CTL is shown in Table 10-53.

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Timer Control

Table 10-53 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2RSTW0hChannel 2 reset.
0h = No effect.
1h = Reset C2CC, PC2CC, and C2CFG.
9C1RSTW0hChannel 1 reset.
0h = No effect.
1h = Reset C1CC, PC1CC, and C1CFG.
8C0RSTW0hChannel 0 reset.
0h = No effect.
1h = Reset C0CC, PC0CC, and C0CFG.
7-6RESERVEDR0hReserved
5INTPR/W0hInterrupt Phase.
This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set.
0h = RIS.TGT and RIS.ZERO are set one system clock cycle after CNTR = TARGET/ZERO.
1h = RIS.TGT and RIS.ZERO are set one timer clock cycle after CNTR = TARGET/ZERO.
4-3CMPDIRR/W0hCompare direction.
This bit field controls the direction the counter must have in order to set the RIS.CnCC channel interrupts. This bitfield is only relevant if [CnCFG.CCACT] is configured to a compare action.
0h = Compare RIS fields are set on up count and down count.
1h = Compare RIS fields are only set on up count.
2h = Compare RIS fields are only set on down count.
3h = RESERVED
2-0MODER/W0hTimer mode control
The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER.
When writing MODE all internally queued updates to the channels and TGT is cleared.
When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example C0CFG.
0h = Disable timer. Updates to counter, channels, and events stop.
1h = Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS.
2h = Count up periodically. The timer increments from 0 to target value, repeatedly.
Period = (target value + 1) * timer clock period
3h = Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly.
Period = (target value * 2) * timer clock period
4h = The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectivly as PHA, PHB and IDX inputs. IDX can be turned off by setting C2CFG.EDGE = NONE.
The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in PRECFG.
5h = Start counting up once synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_ONCE automatically.
It then functions as a normal timer in CTL.MODE = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS.
6h = Start counting up periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_PER automatically.
It then operates as a normal timer in CTL.MODE = UP_PER, incrementing from 0 to target value, repeatedly.
Period = (target value * 2) * timer clock period
7h = Start counting up and down periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UPDWN_PER automatically.
It then operates as a normal timer in CTL.MODE = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly.
Period = (target value * 2) * timer clock period

10.6.5 OUTCTL Register (Offset = 10h) [Reset = 00000000h]

OUTCTL is shown in Table 10-54.

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Output Control
Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected.
An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time.
All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an aditional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see IOCTL.

Table 10-54 OUTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5SETOUT2W0hSet output 2.
Write 1 to set output 2.
4CLROUT2W0hClear output 2.
Write 1 to clear output 2.
3SETOUT1W0hSet output 1.
Write 1 to set output 1.
2CLROUT1W0hClear output 1.
Write 1 to clear output 1.
1SETOUT0W0hSet output 0.
Write 1 to set output 0.
0CLROUT0W0hClear output 0.
Write 1 to clear output 0.

10.6.6 CNTR Register (Offset = 14h) [Reset = 00000000h]

CNTR is shown in Table 10-55.

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Counter
The counter of this timer. After CTL.MODE is set the counter updates at the rate specified in PRECFG.

Table 10-55 CNTR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCurrent counter value.
If CTL.MODE = QDEC this can be used to set the initial counter value during QDEC. Writing to CNTR in other modes than QDEC is possible, but may result in unpredictable behavior.

10.6.7 PRECFG Register (Offset = 18h) [Reset = 00000000h]

PRECFG is shown in Table 10-56.

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Clock Prescaler Configuration
This register is used to set the timer clock period. The prescaler is a counter which counts down from the value TICKDIV. When the prescaler counter reaches zero, CNTR is updated. The field TICKDIV effectively divides the prescaler tick source. The timer clock frequency can be calculated as TICKSRC/(TICKDIV+1).

Table 10-56 PRECFG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8TICKDIVR/W0hTick division.
TICKDIV determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by TICKSRC divided by (TICKDIV + 1). This inverse is the timer clock period.
0x00: Divide by 1.
0x01: Divide by 2.
...
0xFF: Divide by 256.
7-2RESERVEDR0hReserved
1-0TICKSRCR/W0hPrescaler tick source.
TICKSRC determines the source which decrements the prescaler.
0h = Prescaler is updated at the system clock.
1h = Prescaler is updated at the rising edge of TICKEN.
2h = Prescaler is updated at the falling edge of TICKEN.
3h = Prescaler is updated at both edges of TICKEN.

10.6.8 PREEVENT Register (Offset = 1Ch) [Reset = 00000000h]

PREEVENT is shown in Table 10-57.

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Prescaler Event
This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.

Table 10-57 PREEVENT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hSets the HIGH time of the prescaler event output.
Event goes high when the prescaler counter equals VAL. Event goes low when prescaler counter is 0.
Note:
- Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC.
- If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer.

10.6.9 CHFILT Register (Offset = 20h) [Reset = 00000000h]

CHFILT is shown in Table 10-58.

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Channel Input Filter
This register is used to configure the filter on the channel inputs. The configuration is for all inputs.
The filter is enabled when a channel is in capture mode.
The input to the filter is passed to the edge detection logic if LOAD + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample.
If two consecutive samples are unequal, the filter counter restarts from LOAD.
If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic.
The channel filter should only be configured while the CTL.MODE = DIS. Configuring the filter while the timer is running can result in unexpected behavior.

Table 10-58 CHFILT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8LOADR/W0hThe input of the channel filter is passed to the edge detection logic after LOAD + 1 consecutive equal samples.
7-2RESERVEDR0hReserved
1-0MODER/W0hChannel filter mode
0h = Filter is bypassed. No Filter is used.
1h = Filter is clocked by system clock.
2h = Filter is clocked by PRECFG.TICKSRC.
3h = Filter is clocked by timer clock.

10.6.10 FAULT Register (Offset = 24h) [Reset = 00000000h]

FAULT is shown in Table 10-59.

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Fault
This register is used to configure the fault input logic.
Primary use scenario is to select CTL before starting the timer. Follow these steps to configure CTL while CTL.MODE is different from DIS:
- Set C0CFG.EDGE to NONE.
- Configure CTL.
- Wait for three system clock periods before setting C0CFG.EDGE different from NONE.
These steps prevent fault detection caused by expired signal values in synchronizers and edge-detection circuit.

Table 10-59 FAULT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CTLR/W0hFault control
On active fault input the counter can optionally stop. If the counter stops this is done by hardware, software must then restart the timer if wanted. The fault input overrides channel 0 IOC input when CTL != DIS.
This means that channel 0 receives fault as input signal when C0CFG.INPUT = IO and CTL != DIS.
CHFILT can be used to avoid glitching on the fault input. Fault is level triggered, the polarity is set by the C0CFG.EDGE field. Here C0CFG.EDGE = RISE gives active high and C0CFG.EDGE = FALL gives active low polarity.
Fault is typically used together with PARK to stop the PWM signal to an external motor control circuit safely. Configure PARK to ensure predefined values of the PWM outputs.
If CTL != DIS the RIS.FAULT interrupt is set immediately when the fault input is active while CTL.MODE != DIS.
The three modes of fault is described below:
CTL = IMMEDIATE
In this mode the counter stops immediately on an active fault input. This is done by hardware by setting CTL.MODE = DIS. To start the counter software must set CTL.MODE != DIS.
When the counter has stopped, the input synchronizers and the channel filter is not running. This means that if RIS.FAULT is cleared it will not be set again while CTL.MODE = DIS.
CTL = ZEROCOND
In this mode the counter stops when CNTR = 0 after an active fault input. If the RIS.FAULT interrupt has been cleared by software before CNTR = 0, and the fault input is inactive, the counter will continue as normal.
When the counter stops on zero, it can be started again by clearing the RIS.FAULT interrupt if the fault input is inactive. To change the counter mode set CTL.MODE = DIS, clear the RIS.FAULT interrupt, then start timer in wanted mode.
CTL = IRQ
In this mode only the RIS.FAULT flag is set on an active fault input.
0h = Disable. The timer ignores fault.
1h = Immediate reaction. The counter stops immediately on fault.
2h = Zero condition. The counter stops when CNTR = 0.
3h = Interrupt request. Only set RIS.FAULT on active fault.

10.6.11 PARK Register (Offset = 28h) [Reset = 00000000h]

PARK is shown in Table 10-60.

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Park
This register configures how the outputs should be set in Park mode. Park mode is either entered by debug halt or fault. Park mode is activated when the counter stops. Park mode is inactive when the counter starts. When park mode is active all outputs are set to their predefined states.
For IO output signals which have enabled dead band, a dead band insertion will be done before switching to the predefined state.

Table 10-60 PARK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7IOCPS2R/W0hIO Complementary Park State 2
Park state for IO Complementary output 2.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
6IOPS2R/W0hIO Park State 2
Park state for IO output 2.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
5IOCPS1R/W0hIO Complementary Park State 1
Park state for IO Complementary output 1.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
4IOPS1R/W0hIO Park State 1
Park state for IO output 1.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
3IOCPS0R/W0hIO Complementary Park State 0
Park state for IO Complementary output 0.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
2IOPS0R/W0hIO Park State 0
Park state for IO output 0.
0h = Output is set low in park mode.
1h = Output is set high in park mode.
1-0CTLR/W0hPark Control.
0h = Disable park mode.
1h = Enter park mode on fault.
2h = Enter park mode on debug.
3h = Enter parkmode on fault or debug.

10.6.12 DBDLY Register (Offset = 2Ch) [Reset = 00000000h]

DBDLY is shown in Table 10-61.

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Dead Band Delay
This register is used to insert a dead band delay when generating complementary PWM signals. To enable dead band, on for example IO output 0, create a reference PWM signal on Output 0, then set DBCTL.IOC0 = EN.
TBD: 12-bit width fall delay and rise delay may be excessive, if 8-bits are enough we can join DBDLY and DBCTL.

Table 10-61 DBDLY Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-16FALLDLYR/W0hFall delay.
The number of system clock periods inserted between the fall of the dead band reference signal and the rise of the inverted output signal.
15-12RESERVEDR0hReserved
11-0RISEDLYR/W0hRise delay.
The number of system clock periods inserted between the rise of the dead band reference signal and the rise of the output signal.

10.6.13 DBCTL Register (Offset = 30h) [Reset = 00000000h]

DBCTL is shown in Table 10-62.

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Dead Band Control
This register is used to enable dead band for IOC outputs.

Table 10-62 DBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2IO2R/W0hEnable dead band on IO and IO complementary output 2.
0h = Disable
1h = Enable
1IO1R/W0hEnable dead band on IO and IO complementary output 1.
0h = Disable
1h = Enable
0IO0R/W0hEnable dead band on IO and IO complementary output 0.
0h = Disable
1h = Enable

10.6.14 DMA Register (Offset = 3Ch) [Reset = 00000000h]

DMA is shown in Table 10-63.

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Direct Memory Accsess
This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write).
Choose DMA request source by setting the REQ field. The setting of the corresponding interrupt in the RIS registers also sets the DMA request.
Upon a DMA request defined by REQ an internal address pointer is set to RWADDR*4. Every access to DMARW will increment the internal pointer by 4 such that the next DMA access will be to the next register.
The internal pointer will stop after RWCNTR increments. Further access will be ignored.

Table 10-63 DMA Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16RWCNTRR/W0hThe read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the DMARW register. For each DMA access to DMARW an internal counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR is the final register address which can be accessed by the DMA.
15RESERVEDR0hReserved
14-8RWADDRR/W0hThe base address which the DMA access when reading/writing DMARW. The base address is set by taking the 9 LSB of the physical address and divide by 4.
For example, if you wanted the RWADDR to point to the PTGT register you should set RWADDR = 0x0FC/4.
7-4RESERVEDR0hReserved
3-0REQR/W0h
0h = Disabled
1h = Setting of RIS.TGT generates a DMA request.
2h = Setting of RIS.ZERO generates a DMA request.
3h = Setting of RIS.FAULT generates a DMA request.
4h = Setting of RIS.C0CC generates a DMA request.
5h = Setting of RIS.C1CC generates a DMA request.
6h = Setting of RIS.C2CC generates a DMA request.
7h = Setting of RIS.C3CC generates a DMA request.
8h = Setting of RIS.C4CC generates a DMA request.
9h = Setting of RIS.C5CC generates a DMA request.
Ah = Setting of RIS.C6CC generates a DMA request.
Bh = Setting of RIS.C7CC generates a DMA request.
Ch = Setting of RIS.C8CC generates a DMA request.
Dh = Setting of RIS.C9CC generates a DMA request.
Eh = Setting of RIS.C10CC generates a DMA request.
Fh = Setting of RIS.C11CC generates a DMA request.

10.6.15 DMARW Register (Offset = 40h) [Reset = 00000000h]

DMARW is shown in Table 10-64.

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Direct Memory Access
This register is used by the DMA to access (read/write) register inside this LGPT module.
Each access to this register will increment the internal DMA address counter. See DMA for description.

Table 10-64 DMARW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hDMA read write value.
The value that is read/written from/to the registers.

10.6.16 ADCTRG Register (Offset = 44h) [Reset = 00000000h]

ADCTRG is shown in Table 10-65.

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ADC Trigger
This register is used to enable ADC trigger from the timer.
Choose ADC trigger source by setting the SRC field. The setting of the corresponding interrupt in the RIS registers also sets the ADC trigger.

Table 10-65 ADCTRG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0SRCR/W0h
0h = Disabled
1h = Setting of RIS.TGT generates an ADC trigger.
2h = Setting of RIS.ZERO generates an ADC trigger.
3h = Setting of RIS.FAULT generates an ADC trigger.
4h = Setting of RIS.C0CC generates an ADC trigger.
5h = Setting of RIS.C1CC generates an ADC trigger.
6h = Setting of RIS.C2CC generates an ADC trigger.
7h = Setting of RIS.C3CC generates an ADC trigger.
8h = Setting of RIS.C4CC generates an ADC trigger.
9h = Setting of RIS.C5CC generates an ADC trigger.
Ah = Setting of RIS.C6CC generates an ADC trigger.
Bh = Setting of RIS.C7CC generates an ADC trigger.
Ch = Setting of RIS.C8CC generates an ADC trigger.
Dh = Setting of RIS.C9CC generates an ADC trigger.
Eh = Setting of RIS.C10CC generates an ADC trigger.
Fh = Setting of RIS.C11CC generates an ADC trigger.

10.6.17 IOCTL Register (Offset = 48h) [Reset = 00000000h]

IOCTL is shown in Table 10-66.

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IO Controller
This register overrides the IO outputs.

Table 10-66 IOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-10COUT2R/W0hIO complementary output 2 control
This bit field controls IO complementary output 2.
0h = Normal output. The IO complementary output is not changed.
1h = Driven low. The IO complementary output is driven low.
2h = Driven high. The IO complementary output is driven high.
3h = Inverted value. The IO complementary output is inverted.
9-8OUT2R/W0hIO output 2 control
This bit field controls IO output 2.
0h = Normal output. The IO output is not changed.
1h = Driven low. The IO output is driven low.
2h = Driven high. The IO output is driven high.
3h = Inverted value. The IO output is inverted.
7-6COUT1R/W0hIO complementary output 1 control
This bit field controls IO complementary output 1.
0h = Normal output. The IO complementary output is not changed.
1h = Driven low. The IO complementary output is driven low.
2h = Driven high. The IO complementary output is driven high.
3h = Inverted value. The IO complementary output is inverted.
5-4OUT1R/W0hIO output 1 control
This bit field controls IO output 1.
0h = Normal output. The IO output is not changed.
1h = Driven low. The IO output is driven low.
2h = Driven high. The IO output is driven high.
3h = Inverted value. The IO output is inverted.
3-2COUT0R/W0hIO complementary output 0 control
This bit field controls IO complementary output 0.
0h = Normal output. The IO complementary output is not changed.
1h = Driven low. The IO complementary output is driven low.
2h = Driven high. The IO complementary output is driven high.
3h = Inverted value. The IO complementary output is inverted.
1-0OUT0R/W0hIO output 0 control
This bit field controls IO output 0.
0h = Normal output. The IO output is not changed.
1h = Driven low. The IO output is driven low.
2h = Driven high. The IO output is driven high.
3h = Inverted value. The IO output is inverted.

10.6.18 IMASK Register (Offset = 68h) [Reset = 00000000h]

IMASK is shown in Table 10-67.

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Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 10-67 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCR/W0hEnable RIS.C2CC interrupt.
0h = Disable
1h = Enable
9C1CCR/W0hEnable RIS.C1CC interrupt.
0h = Disable
1h = Enable
8C0CCR/W0hEnable RIS.C0CC interrupt.
0h = Disable
1h = Enable
7RESERVEDR0hReserved
6FAULTR/W0hEnable RIS.FAULT interrupt.
0h = Disable
1h = Enable
5IDXR/W0hEnable RIS.IDX interrupt.
0h = Disable
1h = Enable
4DIRCHNGR/W0hEnable RIS.DIRCHNG interrupt.
0h = Disable
1h = Enable
3CNTRCHNGR/W0hEnable RIS.CNTRCHNG interrupt.
0h = Disable
1h = Enable
2DBLTRANSR/W0hEnable RIS.DBLTRANS interrupt.
0h = Disable
1h = Enable
1ZEROR/W0hEnable RIS.ZERO interrupt.
0h = Disable
1h = Enable
0TGTR/W0hEnable RIS.TGT interrupt.
0h = Disable
1h = Enable

10.6.19 RIS Register (Offset = 6Ch) [Reset = 00000000h]

RIS is shown in Table 10-68.

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Raw interrupt status.
This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 10-68 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCR0hStatus of the C2CC interrupt. The interrupt is set when C2CC has capture or compare event.
0h = Cleared
1h = Set
9C1CCR0hStatus of the C1CC interrupt. The interrupt is set when C1CC has capture or compare event.
0h = Cleared
1h = Set
8C0CCR0hStatus of the C0CC interrupt. The interrupt is set when C0CC has capture or compare event.
0h = Cleared
1h = Set
7RESERVEDR0hReserved
6FAULTR0hStatus of the FAULT interrupt. The interrupt is set immediately on active fault input.
0h = Cleared
1h = Set
5IDXR0hStatus of the IDX interrupt. The interrupt is set when IDX is active.
0h = Cleared
1h = Set
4DIRCHNGR0hStatus of the DIRCHNG interrupt. The interrupt is set when the direction of the counter changes.
0h = Cleared
1h = Set
3CNTRCHNGR0hStatus of the CNTRCHNG interrupt. The interrupt is set when the counter increments or decrements.
0h = Cleared
1h = Set
2DBLTRANSR0hStatus of the DBLTRANS interrupt. The interrupt is set when a double transition has happened during QDEC mode.
0h = Cleared
1h = Set
1ZEROR0hStatus of the ZERO interrupt. The interrupt is set when CNTR = 0.
0h = Cleared
1h = Set
0TGTR0hStatus of the TGT interrupt. The interrupt is set when CNTR = TGT.
0h = Cleared
1h = Set

10.6.20 MIS Register (Offset = 70h) [Reset = 00000000h]

MIS is shown in Table 10-69.

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Masked interrupt status.
This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 10-69 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCR0hMasked status of the RIS.C2CC interrupt.
0h = Cleared
1h = Set
9C1CCR0hMasked status of the RIS.C1CC interrupt.
0h = Cleared
1h = Set
8C0CCR0hMasked status of the RIS.C0CC interrupt.
0h = Cleared
1h = Set
7RESERVEDR0hReserved
6FAULTR0hMasked status of the RIS.FAULT interrupt.
0h = Cleared
1h = Set
5IDXR0hMasked status of the RIS.IDX interrupt.
0h = Cleared
1h = Set
4DIRCHNGR0hMasked status of the RIS.DIRCHNG interrupt.
0h = Cleared
1h = Set
3CNTRCHNGR0hMasked status of the RIS.CNTRCHNG interrupt.
0h = Cleared
1h = Set
2DBLTRANSR0hMasked status of the RIS.DBLTRANS interrupt.
0h = Cleared
1h = Set
1ZEROR0hMasked status of the RIS.ZERO interrupt.
0h = Cleared
1h = Set
0TGTR0hMasked status of the RIS.TGT interrupt.
0h = Cleared
1h = Set

10.6.21 ISET Register (Offset = 74h) [Reset = 00000000h]

ISET is shown in Table 10-70.

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Interrupt set register.
This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 10-70 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCW0hSet the RIS.C2CC interrupt.
0h = No effect
1h = Set
9C1CCW0hSet the RIS.C1CC interrupt.
0h = No effect
1h = Set
8C0CCW0hSet the RIS.C0CC interrupt.
0h = No effect
1h = Set
7RESERVEDR0hReserved
6FAULTW0hSet the RIS.FAULT interrupt.
0h = No effect
1h = Set
5IDXW0hSet the RIS.IDX interrupt.
0h = No effect
1h = Set
4DIRCHNGW0hSet the RIS.DIRCHNG interrupt.
0h = No effect
1h = Set
3CNTRCHNGW0hSet the RIS.CNTRCHNG interrupt.
0h = No effect
1h = Set
2DBLTRANSW0hSet the RIS.DBLTRANS interrupt.
0h = No effect
1h = Set
1ZEROW0hSet the RIS.ZERO interrupt.
0h = No effect
1h = Set
0TGTW0hSet the RIS.TGT interrupt.
0h = No effect
1h = Set

10.6.22 ICLR Register (Offset = 78h) [Reset = 00000000h]

ICLR is shown in Table 10-71.

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Interrupt clear register.
This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 10-71 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCW0hClear the RIS.C2CC interrupt.
0h = No effect
1h = Clear
9C1CCW0hClear the RIS.C1CC interrupt.
0h = No effect
1h = Clear
8C0CCW0hClear the RIS.C0CC interrupt.
0h = No effect
1h = Clear
7RESERVEDR0hReserved
6FAULTW0hClear the RIS.FAULT interrupt.
0h = No effect
1h = Clear
5IDXW0hClear the RIS.IDX interrupt.
0h = No effect
1h = Clear
4DIRCHNGW0hClear the RIS.DIRCHNG interrupt.
0h = No effect
1h = Clear
3CNTRCHNGW0hClear the RIS.CNTRCHNG interrupt.
0h = No effect
1h = Clear
2DBLTRANSW0hClear the RIS.DBLTRANS interrupt.
0h = No effect
1h = Clear
1ZEROW0hClear the RIS.ZERO interrupt.
0h = No effect
1h = Clear
0TGTW0hClear the RIS.TGT interrupt.
0h = No effect
1h = Clear

10.6.23 IMSET Register (Offset = 7Ch) [Reset = 00000000h]

IMSET is shown in Table 10-72.

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Interrupt mask set register.
Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 10-72 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCW0hSet the MIS.C2CC mask.
0h = No effect
1h = Set
9C1CCW0hSet the MIS.C1CC mask.
0h = No effect
1h = Set
8C0CCW0hSet the MIS.C0CC mask.
0h = No effect
1h = Set
7RESERVEDR0hReserved
6FAULTW0hSet the MIS.FAULT mask.
0h = No effect
1h = Set
5IDXW0hSet the MIS.IDX mask.
0h = No effect
1h = Set
4DIRCHNGW0hSet the MIS.DIRCHNG mask.
0h = No effect
1h = Set
3CNTRCHNGW0hSet the MIS.CNTRCHNG mask.
0h = No effect
1h = Set
2DBLTRANSW0hSet the MIS.DBLTRANS mask.
0h = No effect
1h = Set
1ZEROW0hSet the MIS.ZERO mask.
0h = No effect
1h = Set
0TGTW0hSet the MIS.TGT mask.
0h = No effect
1h = Set

10.6.24 IMCLR Register (Offset = 80h) [Reset = 00000000h]

IMCLR is shown in Table 10-73.

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Interrupt mask clear register.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 10-73 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10C2CCW0hClear the MIS.C2CC mask.
0h = No effect
1h = Clear
9C1CCW0hClear the MIS.C1CC mask.
0h = No effect
1h = Clear
8C0CCW0hClear the MIS.C0CC mask.
0h = No effect
1h = Clear
7RESERVEDR0hReserved
6FAULTW0hClear the MIS.FAULT mask.
0h = No effect
1h = Clear
5IDXW0hClear the MIS.IDX mask.
0h = No effect
1h = Clear
4DIRCHNGW0hClear the MIS.DIRCHNG mask.
0h = No effect
1h = Clear
3CNTRCHNGW0hClear the MIS.CNTRCHNG mask.
0h = No effect
1h = Clear
2DBLTRANSW0hClear the MIS.DBLTRANS mask.
0h = No effect
1h = Clear
1ZEROW0hClear the MIS.ZERO mask.
0h = No effect
1h = Clear
0TGTW0hClear the MIS.TGT mask.
0h = No effect
1h = Clear

10.6.25 EMU Register (Offset = 84h) [Reset = 00000000h]

EMU is shown in Table 10-74.

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Debug control
This register can be used to freeze the timer when CPU halts when HALT is set to 1. When HALT is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, PARK, if the timer has this register, should be configured additionally. If this timer does not have the PARK register a predefined output value during CPU halt is not possible.

Table 10-74 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CTLR/W0hHalt control.
Configure when the counter shall stop upon CPU halt. This bitfield only applies if HALT = 1.
0h = Immediate reaction. The counter stops immediately on debug halt.
1h = Zero condition. The counter stops when CNTR = 0.
0HALTR/W0hHalt LGPT when CPU is halted in debug.
0h = Disable.
1h = Enable.

10.6.26 C0CFG Register (Offset = C0h) [Reset = 00000000h]

C0CFG is shown in Table 10-75.

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Channel 0 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 10-75 C0CFG Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10OUT2R/W0hOutput 2 enable.
When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
0h = Channel 0 does not control output 2.
1h = Channel 0 controls output 2.
9OUT1R/W0hOutput 1 enable.
When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
0h = Channel 0 does not control output 1.
1h = Channel 0 controls output 1.
8OUT0R/W0hOutput 0 enable.
When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
0h = Channel 0 does not control output 0.
1h = Channel 0 controls output 0.
7RESERVEDR0hReserved
6INPUTR/W0hSelect channel input.
0h = Event fabric
1h = IO controller
5-4EDGER/W0hDetermines the edge that triggers the channel input event. This happens post filter.
0h = Input is turned off.
1h = Input event is triggered at rising edge.
2h = Input event is triggered at falling edge.
3h = Input event is triggered at both edges.
3-0CCACTR/W0hCapture-Compare action.
Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C0CC.
0h = Disable channel.
1h = Set on capture, and then disable channel.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL.
- Disable channel.
Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
2h = Clear on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0.
3h = Set on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0.
4h = Clear on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
5h = Set on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
6h = Toggle on compare, and then disable channel.
Channel function sequence:
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
7h = Pulse on compare, and then disable channel.
Channel function sequence:
- Pulse enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
The output is high for two timer clock periods.
8h = Period and pulse width measurement.
Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.
Set enabled outputs and RIS.C0CC when C0CC.VAL contains signal period and PC0CC.VAL contains signal pulse width.
Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C0CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.
Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
9h = Set on capture repeatedly.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL.
Ah = Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
When C0CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C0CC.VAL / TGT.VAL ).
When C0CC.VAL > TGT.VAL:
Duty cycle = 0.
Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0.
Bh = Set on zero, toggle on compare repeatedly.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
When C0CC.VAL <= TGT.VAL:
Duty cycle = C0CC.VAL / ( TGT.VAL + 1 ).
When C0CC.VAL > TGT.VAL:
Duty cycle = 1.
Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0.
Ch = Clear on compare repeatedly.
Channel function sequence:
- Clear enabled outputs when C0CC.VAL = CNTR.VAL.
Dh = Set on compare repeatedly.
Channel function sequence:
- Set enabled outputs when C0CC.VAL = CNTR.VAL.
Eh = Toggle on compare repeatedly.
Channel function sequence:
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
Fh = Pulse on compare repeatedly.
Channel function sequence:
- Pulse enabled outputs when C0CC.VAL = CNTR.VAL.
The output is high for two timer clock periods.

10.6.27 C1CFG Register (Offset = C4h) [Reset = 00000000h]

C1CFG is shown in Table 10-76.

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Channel 1 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 10-76 C1CFG Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10OUT2R/W0hOutput 2 enable.
When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
0h = Channel 1 does not control output 2.
1h = Channel 1 controls output 2.
9OUT1R/W0hOutput 1 enable.
When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
0h = Channel 1 does not control output 1.
1h = Channel 1 controls output 1.
8OUT0R/W0hOutput 0 enable.
When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
0h = Channel 1 does not control output 0.
1h = Channel 1 controls output 0.
7RESERVEDR0hReserved
6INPUTR/W0hSelect channel input.
0h = Event fabric
1h = IO controller
5-4EDGER/W0hDetermines the edge that triggers the channel input event. This happens post filter.
0h = Input is turned off.
1h = Input event is triggered at rising edge.
2h = Input event is triggered at falling edge.
3h = Input event is triggered at both edges.
3-0CCACTR/W0hCapture-Compare action.
Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C1CC.
0h = Disable channel.
1h = Set on capture, and then disable channel.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL.
- Disable channel.
Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
2h = Clear on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0.
3h = Set on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0.
4h = Clear on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
5h = Set on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
6h = Toggle on compare, and then disable channel.
Channel function sequence:
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
7h = Pulse on compare, and then disable channel.
Channel function sequence:
- Pulse enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
The output is high for two timer clock periods.
8h = Period and pulse width measurement.
Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.
Set enabled outputs and RIS.C1CC when C1CC.VAL contains signal period and PC1CC.VAL contains signal pulse width.
Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C1CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.
Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
9h = Set on capture repeatedly.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL.
Ah = Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
When C1CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C1CC.VAL / TGT.VAL ).
When C1CC.VAL > TGT.VAL:
Duty cycle = 0.
Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0.
Bh = Set on zero, toggle on compare repeatedly.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
When C1CC.VAL <= TGT.VAL:
Duty cycle = C1CC.VAL / ( TGT.VAL + 1 ).
When C1CC.VAL > TGT.VAL:
Duty cycle = 1.
Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0.
Ch = Clear on compare repeatedly.
Channel function sequence:
- Clear enabled outputs when C1CC.VAL = CNTR.VAL.
Dh = Set on compare repeatedly.
Channel function sequence:
- Set enabled outputs when C1CC.VAL = CNTR.VAL.
Eh = Toggle on compare repeatedly.
Channel function sequence:
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
Fh = Pulse on compare repeatedly.
Channel function sequence:
- Pulse enabled outputs when C1CC.VAL = CNTR.VAL.
The output is high for two timer clock periods.

10.6.28 C2CFG Register (Offset = C8h) [Reset = 00000000h]

C2CFG is shown in Table 10-77.

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Channel 2 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 10-77 C2CFG Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10OUT2R/W0hOutput 2 enable.
When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
0h = Channel 2 does not control output 2.
1h = Channel 2 controls output 2.
9OUT1R/W0hOutput 1 enable.
When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
0h = Channel 2 does not control output 1.
1h = Channel 2 controls output 1.
8OUT0R/W0hOutput 0 enable.
When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
0h = Channel 2 does not control output 0.
1h = Channel 2 controls output 0.
7RESERVEDR0hReserved
6INPUTR/W0hSelect channel input.
0h = Event fabric
1h = IO controller
5-4EDGER/W0hDetermines the edge that triggers the channel input event. This happens post filter.
0h = Input is turned off.
1h = Input event is triggered at rising edge.
2h = Input event is triggered at falling edge.
3h = Input event is triggered at both edges.
3-0CCACTR/W0hCapture-Compare action.
Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C2CC.
0h = Disable channel.
1h = Set on capture, and then disable channel.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL.
- Disable channel.
Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
2h = Clear on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0.
3h = Set on zero, toggle on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0.
4h = Clear on compare, and then disable channel.
Channel function sequence:
- Clear enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
5h = Set on compare, and then disable channel.
Channel function sequence:
- Set enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
6h = Toggle on compare, and then disable channel.
Channel function sequence:
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
7h = Pulse on compare, and then disable channel.
Channel function sequence:
- Pulse enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
The output is high for two timer clock periods.
8h = Period and pulse width measurement.
Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.
Set enabled outputs and RIS.C2CC when C2CC.VAL contains signal period and PC2CC.VAL contains signal pulse width.
Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C2CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.
Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
9h = Set on capture repeatedly.
Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL.
Ah = Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
When C2CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C2CC.VAL / TGT.VAL ).
When C2CC.VAL > TGT.VAL:
Duty cycle = 0.
Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0.
Bh = Set on zero, toggle on compare repeatedly.
Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
When C2CC.VAL <= TGT.VAL:
Duty cycle = C2CC.VAL / ( TGT.VAL + 1 ).
When C2CC.VAL > TGT.VAL:
Duty cycle = 1.
Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0.
Ch = Clear on compare repeatedly.
Channel function sequence:
- Clear enabled outputs when C2CC.VAL = CNTR.VAL.
Dh = Set on compare repeatedly.
Channel function sequence:
- Set enabled outputs when C2CC.VAL = CNTR.VAL.
Eh = Toggle on compare repeatedly.
Channel function sequence:
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
Fh = Pulse on compare repeatedly.
Channel function sequence:
- Pulse enabled outputs when C2CC.VAL = CNTR.VAL.
The output is high for two timer clock periods.

10.6.29 PTGT Register (Offset = FCh) [Reset = 00000000h]

PTGT is shown in Table 10-78.

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Pipeline Target
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.
If CTL.MODE != QDEC.
Target value for next counter period.
The timer will copy PTGT.VAL to TGT.VAL on the upcoming CNTR zero crossing only if PTGT.VAL has been written. The copy does not happen when restarting the timer.
This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.
If CTL.MODE = QDEC
The CNTR value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, CNTR is loaded with zero on IDX.
In this mode the VALUE is not loaded into TGT on zero crossing.

Table 10-78 PTGT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hThe pipleline target value.

10.6.30 PC0CC Register (Offset = 100h) [Reset = 00000000h]

PC0CC is shown in Table 10-79.

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Pipeline Channel 0 Capture Compare

Table 10-79 PC0CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C0CC interrupt.
Compare mode:
An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE.

10.6.31 PC1CC Register (Offset = 104h) [Reset = 00000000h]

PC1CC is shown in Table 10-80.

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Pipeline Channel 1 Capture Compare

Table 10-80 PC1CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C1CC interrupt.
Compare mode:
An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE.

10.6.32 PC2CC Register (Offset = 108h) [Reset = 00000000h]

PC2CC is shown in Table 10-81.

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Pipeline Channel 2 Capture Compare

Table 10-81 PC2CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C2CC interrupt.
Compare mode:
An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE.

10.6.33 TGT Register (Offset = 13Ch) [Reset = 0000FFFFh]

TGT is shown in Table 10-82.

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Target
User defined counter target.
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.

Table 10-82 TGT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/WFFFFhUser defined counter target value.

10.6.34 C0CC Register (Offset = 140h) [Reset = 00000000h]

C0CC is shown in Table 10-83.

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Channel 0 Capture Compare

Table 10-83 C0CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C0CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value.

10.6.35 C1CC Register (Offset = 144h) [Reset = 00000000h]

C1CC is shown in Table 10-84.

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Channel 1 Capture Compare

Table 10-84 C1CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C1CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value.

10.6.36 C2CC Register (Offset = 148h) [Reset = 00000000h]

C2CC is shown in Table 10-85.

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Channel 2 Capture Compare

Table 10-85 C2CC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will clear the RIS.C2CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value.

10.6.37 PTGTNC Register (Offset = 17Ch) [Reset = 00000000h]

PTGTNC is shown in Table 10-86.

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Pipeline Target No Clear
Use this register to read or write to PTGT without clearing the RIS.ZERO and RIS.TGT interrupt.

Table 10-86 PTGTNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hA read or write to this register will not clear the RIS.TGT interrupt.
If CTL.MODE != QDEC.
Target value for next counter period.
The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not happen when restarting the timer.
This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.
If CTL.MODE = QDEC.
The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when CNTR.VAL becomes 0.

10.6.38 PC0CCNC Register (Offset = 180h) [Reset = 00000000h]

PC0CCNC is shown in Table 10-87.

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Pipeline Channel 0 Capture Compare No Clear

Table 10-87 PC0CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C0CC interrupt.
Compare mode:
An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE.

10.6.39 PC1CCNC Register (Offset = 184h) [Reset = 00000000h]

PC1CCNC is shown in Table 10-88.

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Pipeline Channel 1 Capture Compare No Clear

Table 10-88 PC1CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C1CC interrupt.
Compare mode:
An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE.

10.6.40 PC2CCNC Register (Offset = 188h) [Reset = 00000000h]

PC2CCNC is shown in Table 10-89.

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Pipeline Channel 2 Capture Compare No Clear

Table 10-89 PC2CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hPipeline Capture Compare value.
User defined pipeline compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C2CC interrupt.
Compare mode:
An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
Capture mode:
When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE.

10.6.41 TGTNC Register (Offset = 1BCh) [Reset = 0000FFFFh]

TGTNC is shown in Table 10-90.

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Target No Clear
Use this register to read or write to TGT without clearing the RIS.ZERO and RIS.TGT interrupt.

Table 10-90 TGTNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/WFFFFhUser defined counter target value.

10.6.42 C0CCNC Register (Offset = 1C0h) [Reset = 00000000h]

C0CCNC is shown in Table 10-91.

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Channel 0 Capture Compare No Clear

Table 10-91 C0CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C0CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value.

10.6.43 C1CCNC Register (Offset = 1C4h) [Reset = 00000000h]

C1CCNC is shown in Table 10-92.

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Channel 1 Capture Compare No Clear

Table 10-92 C1CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C1CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value.

10.6.44 C2CCNC Register (Offset = 1C8h) [Reset = 00000000h]

C2CCNC is shown in Table 10-93.

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Channel 2 Capture Compare No Clear

Table 10-93 C2CCNC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hCapture Compare value.
User defined compare value or channel-updated capture value.
A read or write to this register will not clear the RIS.C2CC interrupt.
Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal.
Capture mode:
The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value.