SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The common TX FIFO is a 16-bit wide, 8 location deep, first-in first-out memory buffer, if the selected SPI data frame size is greater than 8 bits. The organization of this FIFO is modified dynamically if the selected data size is less than or equal to 8 bits, and for better FIFO utilization behaves as an 8-bit wide, 16 location deep FIFO. The CPU writes data to the FIFO via the SPI.TXDATA register and data is stored in the FIFO until the data is read out by the transmission logic.
When configured as a controller (or a peripheral), parallel data is written into the TX FIFO before serial conversion and transmission to the attached peripheral (or controller) through the PICO (or POCI) pin.
In peripheral mode, the SPI transmits data each time the controller initiates a transaction. If the TX FIFO is empty and the controller initiates a transaction, the peripheral transmits garbage data. User or software is responsible to make valid data available in the FIFO as needed. The SPI can be configured to generate an interrupt when a configurable level within the FIFO is selected via SPI:IFLS, or a μDMA request when the FIFO is not FULL.