SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The external controller is supposed to always send the number of clocks equal to the DSS value written, before de-asserting CS and ending transmission. In case CS is deactivated before the entire data frame has been sent out by the peripheral, then CSD error bit is set and can be read within SPI.STA[5] CSD. This bit, once set, must be cleared by software.
The TX FIFO full level indicating the number of entries written into the TXFIFO can be read out via the SPI.STA[13:8] TXFIFOLVL bit field.
Additional status bits related to peripheral mode transfer complete, SPI busy indication, TX and RX FIFO flags can be read out from the SPI.STA register. The peripheral mode transfer complete indication bit, once set, must be cleared by software.