Top

Product details

Parameters

DSP 1 C64x Operating systems DSP/BIOS, VLX Video port (configurable) 3 20-Bit Dual-Ch On-chip L2 cache/RAM 256 KB(DSP) DRAM DDR2 PCI/PCIe 1 32-Bit [66 MHz] Ethernet MAC 10/100 I2C 1 Rating Catalog open-in-new Find other Audio & media processors

Package | Pins | Size

FC/CSP (GDK) 548 529 mm² 23 x 23 FCBGA (GNZ) 548 729 mm² 27 x 27 FCBGA (ZDK) 548 529 mm² 23 x 23 FCBGA (ZNZ) 548 729 mm² 27 x 27 open-in-new Find other Audio & media processors

Features

  • High-Performance Digital Media Processor (TMS320DM642)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Three Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Multichannel Audio Serial Port (McASP)
    • Eight Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus™
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/O, 1.2-V Internal (-500)
  • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

open-in-new Find other Audio & media processors

Description

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels - A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VXCO interpolated control port (VIC) provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

open-in-new Find other Audio & media processors
Download

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 92
Type Title Date
* Datasheet TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor datasheet (Rev. N) Oct. 12, 2010
* Errata TMS320DM642 DSP Silicon Errata, Silicon Revisions 2.0, 1.2, 1.1, 1.0 (Rev. K) Feb. 04, 2010
User guides Emulation and Trace Headers Technical Reference Manual (Rev. I) Aug. 09, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C64x DSP Video Port/ VCXO Interpolated Control (VIC) Port Reference Guide (Rev. G) Nov. 12, 2010
User guides TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
Application notes Interfacing a CMOS Sensor to the TMS320DM642 Using Raw Capture Mode (Rev. A) Jan. 27, 2010
User guides TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) Jul. 02, 2009
User guides TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) Nov. 20, 2008
Application notes Migrating from TMS320DM642 to TMS320DM6467 Nov. 17, 2008
Application notes Migrating from TMS320DM642 to TMS320DM648/DM6437 Aug. 19, 2008
Application notes TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) Sep. 04, 2007
Application notes Migrating from TMS320DM642 to TMS320DM6437 Jun. 29, 2007
Application notes Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 Jun. 07, 2007
Application notes Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007
User guides TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) Apr. 11, 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) Apr. 04, 2007
User guides TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) Mar. 26, 2007
User guides TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) Jan. 25, 2007
User guides TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) Dec. 14, 2006
User guides TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) Nov. 15, 2006
User guides TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) Feb. 28, 2006
User guides TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) Jan. 01, 2006
Application notes TMS320DM642 Hardware Designer's Resource Guide (Rev. A) Oct. 25, 2005
Application notes Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005
More literature TMS320DM64x Digital Media Processors - Product Bulletin (Rev. C) Aug. 30, 2005
User guides TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) Mar. 01, 2005
Application notes TMS320DM64x Power Consumption Summary (Rev. F) Feb. 18, 2005
User guides TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) Jan. 25, 2005
Application notes Video Scaling Example on the DM642 EVM Sep. 27, 2004
Application notes Driver Examples on the DM642 EVM (Rev. A) Aug. 31, 2004
Application notes Use and Handling of Semiconductor Packages With ENIG Pad Finishes Aug. 31, 2004
User guides TMS320C6000 Chip Support Library API Reference Guide (Rev. J) Aug. 13, 2004
Application notes JPEG Motion on the DM642 EVM (Rev. A) Jul. 16, 2004
Application notes JPEG Netcam on the DM642 EVM (Rev. A) Jul. 16, 2004
Application notes JPEG Netcam2 on the DM642 EVM (Rev. A) Jul. 16, 2004
Application notes JPEG Network on the DM642 EVM (Rev. A) Jul. 16, 2004
Application notes The TMS320DM642 Video Port Mini-Driver for TVP5146 and TVP5150 decoder Jul. 16, 2004
Application notes High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A) May 03, 2004
Application notes Interfacing an LCD Controller to a DM642 Video Port (Rev. B) May 03, 2004
Application notes TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) Apr. 26, 2004
Application notes TMS320C6000 Board Design: Considerations for Debug (Rev. C) Apr. 21, 2004
User guides TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) Mar. 26, 2004
User guides TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) Mar. 25, 2004
Application notes TMS320C6000 McBSP Initialization (Rev. C) Mar. 08, 2004
Application notes TMS320C6000 EDMA IO Scheduling and Performance Mar. 05, 2004
More literature Video/Imaging Benchmarks (Rev. A) Mar. 01, 2004
More literature Video Security over IP (VSIP) Development Platform Product Bulletin Nov. 05, 2003
Application notes On-Screen-Display Driver Examples For DM642 EVM Demo Software Release Report Oct. 14, 2003
Application notes Adapting the SPRA904 Motion Detection Application Report to the DM642 EVM Oct. 10, 2003
Application notes An Audio Example Using Reference Frameworks on the DM642 EVM Aug. 31, 2003
Application notes Audio Demonstration on the DM642 EVM Aug. 31, 2003
Application notes Audio Echo on the DM642 EVM Aug. 31, 2003
Application notes H.263 Loop Back on the DM642 EVM Aug. 31, 2003
Application notes JPEG Loop Back on the DM642 EVM Aug. 31, 2003
Application notes MPEG-2 Encoder on the DM642 EVM Aug. 31, 2003
Application notes MPEG-2 High Definition Decoder on the DM642 EVM Aug. 31, 2003
Application notes MPEG-2 Loop Back on the DM642 EVM Aug. 31, 2003
Application notes The TMS320DM642 Video Port Mini-Driver (Rev. A) Aug. 14, 2003
User guides TMS320C6000 DSP Designing for JTAG Emulation Reference Guide Jul. 31, 2003
More literature TMS320DM64x Digital Media Development Tools Product Bulletin Jul. 31, 2003
Application notes A DSP/BIOS AIC23 Codec Device Driver for the TMS320DM642 EVM Jun. 30, 2003
User guides TMS320DM642 EVM OSD FPGA User's Guide Jun. 26, 2003
Application notes TMS320DM642 EVM Daughtercard Specification Revision 1.0 Jun. 25, 2003
User guides TMS320C6000 DSP Cache User's Guide (Rev. A) May 05, 2003
Application notes Using IBIS Models for Timing Analysis (Rev. A) Apr. 15, 2003
User guides TMS320DM642 Technical Overview Sep. 13, 2002
Application notes TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) Jun. 04, 2002
Application notes TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) Apr. 17, 2002
Application notes TMS320C6000 Board Design for JTAG (Rev. C) Apr. 02, 2002
Application notes TMS320C6000 EMIF to External Flash Memory (Rev. A) Feb. 13, 2002
Application notes Cache Usage in High-Performance DSP Applications with the TMS320C64x Dec. 13, 2001
Application notes Using a TMS320C6000 McBSP for Data Packing (Rev. A) Oct. 31, 2001
Application notes TMS320C6000 Enhanced DMA: Example Applications (Rev. A) Oct. 24, 2001
Application notes Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) Sep. 30, 2001
Application notes TMS320C6000 Host Port to MC68360 Interface (Rev. A) Sep. 30, 2001
Application notes TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) Aug. 31, 2001
Application notes Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 System Clock Circuit Example (Rev. A) Aug. 15, 2001
Application notes TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) Jul. 23, 2001
Application notes TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) Jul. 10, 2001
Application notes TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) Jun. 30, 2001
Application notes TMS320C6000 Host Port to MPC860 Interface (Rev. A) Jun. 21, 2001
Application notes TMS320C6000 McBSP: IOM-2 Interface (Rev. A) May 21, 2001
User guides TMS320C64x Technical Overview (Rev. B) Jan. 30, 2001
Application notes Circular Buffering on TMS320C6000 (Rev. A) Sep. 12, 2000
Application notes TMS320C6000 McBSP as a TDM Highway (Rev. A) Sep. 11, 2000
Application notes TMS320C6000 u-Law and a-Law Companding with Software or the McBSP Feb. 02, 2000
Application notes General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point Jan. 31, 2000
Application notes TMS320C6000 C Compiler: C Implementation of Intrinsics Dec. 07, 1999
Application notes TMS320C6000 McBSP: I2S Interface Sep. 08, 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
$295.00
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$995.00
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$1,495.00
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TI-RTOS Networking
NDKTCPIP TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for TMS320C6000(TM) High Performance DSP-based devices. 
Features

TI-RTOS Networking includes:

  • Core TCP/IP protocol stack: Dual-mode IPv6/IPv4 stack in both source and binary only including VLAN packet priority marking, TCP, UDP, ICMP, IGMP, IP, and ARP
  • Network applications: HTTP, TELNET, TFTP, DNS, DHCP (IPv4 only) in both source and binary form
  • Serial support: PPP (...)
DRIVERS & LIBRARIES Download
TMS320C6000 Chip Support Library
SPRC090 — The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
DRIVERS & LIBRARIES Download
C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM111.ZIP (110 KB) - IBIS Model
SIMULATION MODELS Download
SPRM112.ZIP (8 KB) - BSDL Model
SIMULATION MODELS Download
SPRM113.ZIP (8 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
FC/CSP (GDK) 548 View options
FCBGA (GNZ) 548 View options
FCBGA (ZDK) 548 View options
FCBGA (ZNZ) 548 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos