Digital media processor, up to 2400 MIPS, 300 MHz clock rate

TMS320DM6431Q

ACTIVE

Product details

DSP 1 C64x DSP MHz (Max) 300 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Automotive Operating temperature range (C) -40 to 125
DSP 1 C64x DSP MHz (Max) 300 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Automotive Operating temperature range (C) -40 to 125
NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6431)
    • 3.33-ns Instruction Cycle Time
    • 300-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 2400 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
      • C64x+ Instruction Set Features
        • Byte-Addressable (8-/16-/32-/64-Bit Data)
        • 8-Bit Overflow Protection
        • Bit-Field Extract, Set, Clear
        • Normalization, Saturation, Bit-Counting
        • VelociTI.2 Increased Orthogonality
        • C64x+ Extensions
          • Compact 16-bit Instructions
          • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (10-Bit) Interface
      • Glueless Interface to Common Video Decoders
  • External Memory Interfaces (EMIFs)
    • 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O)
      • Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • One UART With RTS and CTS Flow Control
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • One Multichannel Buffered Serial Port (McBSP0)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-3/-3Q/-3S)
  • Applications:
    • Digital Media
    • Networked Media Encode
    • Video Imaging

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6431)
    • 3.33-ns Instruction Cycle Time
    • 300-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 2400 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
      • C64x+ Instruction Set Features
        • Byte-Addressable (8-/16-/32-/64-Bit Data)
        • 8-Bit Overflow Protection
        • Bit-Field Extract, Set, Clear
        • Normalization, Saturation, Bit-Counting
        • VelociTI.2 Increased Orthogonality
        • C64x+ Extensions
          • Compact 16-bit Instructions
          • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (10-Bit) Interface
      • Glueless Interface to Common Video Decoders
  • External Memory Interfaces (EMIFs)
    • 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O)
      • Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • One UART With RTS and CTS Flow Control
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • One Multichannel Buffered Serial Port (McBSP0)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-3/-3Q/-3S)
  • Applications:
    • Digital Media
    • Networked Media Encode
    • Video Imaging

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320DM6431 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6431 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6431 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32K-byte (KB) memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data/memory memory/cache (L1D) consists of a 64KB memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 64KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6431 device includes a Video Processing Subsystem (VPSS) with a Video Processing Front-End (VPFE) input used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC). The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs).

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6431 and the network. The DM6431 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C port allows DM6431 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6431 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320DM6431 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6431 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6431 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32K-byte (KB) memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data/memory memory/cache (L1D) consists of a 64KB memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 64KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6431 device includes a Video Processing Subsystem (VPSS) with a Video Processing Front-End (VPFE) input used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC). The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs).

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6431 and the network. The DM6431 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C port allows DM6431 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6431 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet TMS320DM6431 Digital Media Processor datasheet (Rev. C) 06 Jun 2008
* Errata TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. E) 12 Aug 2011
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 13 Aug 2015
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 Aug 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 Aug 2012
Application note Using the TMS320DM643x Bootloader (Rev. E) 23 Mar 2012
User guide TMS320C6000 Programmer's Guide (Rev. K) 11 Jul 2011
User guide TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. E) 25 Mar 2011
User guide TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. C) 12 Jan 2011
User guide TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. C) 23 Dec 2010
User guide TMS320DM643x DMP Video Processing Front End (VPFE) User's Guide (Rev. D) 25 Aug 2010
User guide TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 05 Aug 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
Application note TMS320DM643x Power Consumption Summary (Rev. C) 10 May 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 Mar 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 Mar 2010
User guide TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. C) 16 Dec 2009
Application note Common Object File Format (COFF) 15 Apr 2009
User guide TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. B) 24 Feb 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 Feb 2009
Application note 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 09 Oct 2008
Application note 5Vin DM643x Power using DC/DC Controllers and LDO 09 Oct 2008
Application note 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 09 Oct 2008
Application note 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) 09 Oct 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note Understanding the Davinci Preview Engine (Rev. A) 23 Jul 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
Application note Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) 26 Jun 2008
Application note How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) 16 Jun 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 May 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 May 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 May 2008
User guide TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) 18 Mar 2008
User guide TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) 13 Mar 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 Mar 2008
User guide TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 03 Mar 2008
User guide TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) 05 Feb 2008
Application note How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) 14 Nov 2007
User guide TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) 17 Sep 2007
Application note TMS320DM643x Pin Multiplexing Utility 06 Jul 2007
User guide TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) 25 Jun 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 May 2007
User guide TMS320DM643x DMP High-End CAN Controller (HECC) User's Guide (Rev. A) 15 May 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
More literature DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 13 Feb 2007
More literature Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) 13 Feb 2007
Application note DaVinci Technology Background and Specifications (Rev. A) 04 Jan 2007
User guide TMS320DM643x DMP 64-Bit Timer User's Guide 18 Dec 2006
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 Mar 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 Mar 2006
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Oct 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Application software & framework

TMDMFP — Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support (RTS) Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Software codec

TMDXDAISXDM — eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Simulation model

DM6431 ZWT BSDL Model

SPRM224.ZIP (9 KB) - BSDL Model
Simulation model

DM6431 ZDU BSDL Model

SPRM225.ZIP (10 KB) - BSDL Model
Simulation model

DM6431 ZWT IBIS Model (Rev. B)

SPRM236B.ZIP (267 KB) - IBIS Model
Simulation model

DM6431 ZDU IBIS Model (Rev. B)

SPRM237B.ZIP (267 KB) - IBIS Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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NFBGA (ZWT) 361 View options

Ordering & quality

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  • Ongoing reliability monitoring

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