TMS320C6412

FCBGA (GNZ)

548

729 mm² 27 x 27

FCBGA (ZDK)

548

529 mm² 23 x 23

FCBGA (ZNZ)

548

729 mm² 27 x 27

FCCSP (GDK)

548

529 mm² 23 x 23

High-Performance Digital Media Processor (TMS320C6412)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1024M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface (MII)
- 8 Independent Transmit (TX) and 1 Receive (RX) Channel
Management Data Input/Output (MDIO)
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
Inter-Integrated Circuit (I²C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

High-Performance Digital Media Processor (TMS320C6412)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1024M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface (MII)
- 8 Independent Transmit (TX) and 1 Receive (RX) Channel
Management Data Input/Output (MDIO)
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
Inter-Integrated Circuit (I²C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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Technical documentation

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	Type	Title	Date
*	Data sheet	TMS320C6412 Fixed-Point Digital Signal Processor datasheet (Rev. J)	12 Oct 2010
*	Errata	TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J)	04 Feb 2010
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	19 May 2021
	Technical article	Bringing the next evolution of machine learning to the edge	27 Nov 2018
	Technical article	How quality assurance on the Processor SDK can improve software scalability	22 Aug 2018
	Technical article	Clove: Low-Power video solutions based on Sitara™ AM57x processors	21 Jul 2016
	Technical article	TI's new DSP Benchmark Site	08 Feb 2016
	User guide	Emulation and Trace Headers Technical Reference Manual (Rev. I)	09 Aug 2012
	Application note	Introduction to TMS320C6000 DSP Optimization	06 Oct 2011
	User guide	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)	30 Jul 2010
	User guide	TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)	02 Jul 2009
	Application note	TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)	04 Sep 2007
	Application note	Thermal Considerations for the DM64xx, DM64x, and C6000 Devices	20 May 2007
	User guide	TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)	11 Apr 2007
	More literature	TMS320C6000 DSP TCP/IP Stack Software (Rev. C)	04 Apr 2007
	User guide	TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D)	26 Mar 2007
	User guide	TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C)	25 Jan 2007
	User guide	TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)	14 Dec 2006
	User guide	TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C)	15 Nov 2006
	User guide	TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C)	28 Feb 2006
	User guide	TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)	01 Jan 2006
	Application note	TMS320C6412 Hardware Designer's Resource Guide (Rev. A)	21 Oct 2005
	Application note	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)	20 Oct 2005
	User guide	TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)	01 Mar 2005
	Application note	TMS320C6412 Power Consumption Summary (Rev. E)	27 Jan 2005
	User guide	TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)	25 Jan 2005
	Application note	Use and Handling of Semiconductor Packages With ENIG Pad Finishes	31 Aug 2004
	User guide	TMS320C6000 Chip Support Library API Reference Guide (Rev. J)	13 Aug 2004
	Application note	TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)	26 Apr 2004
	Application note	TMS320C6000 Board Design: Considerations for Debug (Rev. C)	21 Apr 2004
	User guide	TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A)	26 Mar 2004
	User guide	TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A)	25 Mar 2004
	Application note	TMS320C6000 McBSP Initialization (Rev. C)	08 Mar 2004
	Application note	TMS320C6000 EDMA IO Scheduling and Performance	05 Mar 2004
	Application note	TMS320C64x EDMA Performance Data	05 Mar 2004
	Application note	TMS320C64x EDMA Architecture	03 Mar 2004
	Application note	TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance	31 Oct 2003
	Application note	TMS320C64x DSP Host Port Interface (HPI) Performance	24 Oct 2003
	User guide	TMS320C6000 DSP Designing for JTAG Emulation Reference Guide	31 Jul 2003
	User guide	TMS320C6000 DSP Cache User's Guide (Rev. A)	05 May 2003
	Application note	Using IBIS Models for Timing Analysis (Rev. A)	15 Apr 2003
	Application note	TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)	04 Jun 2002
	Application note	TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)	17 Apr 2002
	Application note	TMS320C6000 Board Design for JTAG (Rev. C)	02 Apr 2002
	Application note	TMS320C6000 EMIF to External Flash Memory (Rev. A)	13 Feb 2002
	Application note	Cache Usage in High-Performance DSP Applications with the TMS320C64x	13 Dec 2001
	Application note	Using a TMS320C6000 McBSP for Data Packing (Rev. A)	31 Oct 2001
	Application note	TMS320C6000 Enhanced DMA: Example Applications (Rev. A)	24 Oct 2001
	Application note	Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)	30 Sep 2001
	Application note	TMS320C6000 Host Port to MC68360 Interface (Rev. A)	30 Sep 2001
	Application note	TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)	31 Aug 2001
	Application note	TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)	31 Aug 2001
	Application note	Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)	31 Aug 2001
	Application note	TMS320C6000 System Clock Circuit Example (Rev. A)	15 Aug 2001
	Application note	TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)	23 Jul 2001
	Application note	TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)	10 Jul 2001
	Application note	TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)	30 Jun 2001
	Application note	TMS320C6000 Host Port to MPC860 Interface (Rev. A)	21 Jun 2001
	Application note	TMS320C6000 McBSP: IOM-2 Interface (Rev. A)	21 May 2001
	User guide	TMS320C64x Technical Overview (Rev. B)	30 Jan 2001
	Application note	Circular Buffering on TMS320C6000 (Rev. A)	12 Sep 2000
	Application note	TMS320C6000 McBSP as a TDM Highway (Rev. A)	11 Sep 2000
	Application note	TMS320C6000 u-Law and a-Law Companding with Software or the McBSP	02 Feb 2000
	Application note	General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point	31 Jan 2000
	Application note	TMS320C6000 C Compiler: C Implementation of Intrinsics	07 Dec 1999
	Application note	TMS320C6000 McBSP: I2S Interface	08 Sep 1999

Design & development

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Evaluation board

TMDSDSK6416 — TMS320C6416 DSP Starter Kit (DSK)

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User guide

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Driver or library

SPRC090 — TMS320C6000 Chip Support Library

The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)

Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support (RTS) Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

From: Adaptive Digital Technologies, Inc.

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Software codec

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP, speech, and audio codecs

Since 1999, CouthIT has been helping customers transform their ideas into real-time robust software solutions. They license specialized, pre-built, highly optimized software modules in the areas of VoIP and speech and audio codecs, and provide software optimization and customization services for (...)

From: Couth Infotech Pvt. Ltd.

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Software codec

VOCAL-3P-DSPVOIPCODECS — Vocal technologies DSP VoIP codecs

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

From: VOCAL Technologies, Ltd.

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Simulation model

C6412 GDK/GNZ IBIS Model

SPRM110.ZIP (109 KB) - IBIS Model

Simulation model

C6412 GNZ BSDL Model

SPRM122.ZIP (9 KB) - BSDL Model

Simulation model

C6412 GDK BSDL Model

SPRM123.ZIP (9 KB) - BSDL Model

Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)