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Digital Media Processor

TMS320DM6437

ACTIVE

Product details

Parameters

Arm CPU 0 Arm MHz (Max.) 0 DSP 1 C64x Operating system DSP/BIOS, VLX Video acceleration 0 Video port (configurable) 1 Dedicated Input, 1 Dedicated Output On-chip L2 cache/RAM 128 KB (DSP) DRAM DDR2 PCI/PCIe 1 32-Bit [33 MHz] Ethernet MAC 10/100 USB 0 SPI 0 I2C 1 UART (SCI) 2 Operating temperature range (C) 0 to 90 Rating Catalog open-in-new Find other Audio & media processors

Package | Pins | Size

BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16 open-in-new Find other Audio & media processors

Features

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6437)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  • Load-Store Architecture With Non-Aligned Support
  • 64 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Additional C64x+™ Enhancements
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
    • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS)
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) Bus and Interfaces With DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus×)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • High-End CAN Controller (HECC)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • Applications
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

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Description

The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6437 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6437 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6437. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6437 and the network. The DM6437 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6437 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6437 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Datasheet TMS320DM6437 Digital Media Processor datasheet (Rev. D) Jun. 06, 2008
* Errata TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. E) Aug. 12, 2011
Application notes Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug. 13, 2015
User guides TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug. 21, 2012
User guides TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug. 21, 2012
Application notes Using the TMS320DM643x Bootloader (Rev. E) Mar. 23, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C6000 Programmer's Guide (Rev. K) Jul. 11, 2011
User guides TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. E) Mar. 25, 2011
User guides TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. C) Jan. 12, 2011
User guides TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. C) Dec. 23, 2010
User guides TMS320DM643x DMP Video Processing Front End (VPFE) User's Guide (Rev. D) Aug. 25, 2010
User guides TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. B) Aug. 05, 2010
User guides TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) Aug. 03, 2010
User guides TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
User guides TMS320DM643x DMP Peripheral Component Interconnect (PCI) User's Guide (Rev. C) May 14, 2010
Application notes TMS320DM643x Power Consumption Summary (Rev. C) May 10, 2010
User guides TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) Mar. 18, 2010
User guides TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) Mar. 18, 2010
User guides TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. C) Dec. 16, 2009
Application notes Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB Nov. 25, 2009
Application notes Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms Sep. 24, 2009
Application notes Common Object File Format (COFF) Apr. 15, 2009
User guides TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. B) Feb. 24, 2009
User guides TMS320C64x+ DSP Cache User's Guide (Rev. B) Feb. 11, 2009
Application notes 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO Oct. 09, 2008
Application notes 5Vin DM643x Power using DC/DC Controllers and LDO Oct. 09, 2008
Application notes 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO Oct. 09, 2008
Application notes 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) Oct. 09, 2008
Application notes Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) Aug. 21, 2008
Application notes Migrating from TMS320DM642 to TMS320DM648/DM6437 Aug. 19, 2008
Application notes Understanding the Davinci Preview Engine (Rev. A) Jul. 23, 2008
Application notes Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008
Application notes Understanding the Davinci Resizer (Rev. B) Jul. 17, 2008
User guides TMS320DM643x DMP Host Port Interface (HPI) User's Guide (Rev. D) Jul. 16, 2008
Application notes Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) Jun. 26, 2008
Application notes How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) Jun. 16, 2008
User guides TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) May 15, 2008
User guides TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) May 15, 2008
User guides TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) May 05, 2008
User guides TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) Mar. 18, 2008
User guides TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) Mar. 13, 2008
User guides TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) Mar. 06, 2008
User guides TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) Mar. 03, 2008
User guides TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) Feb. 05, 2008
Application notes Installing ObjectVideo OnBoard With the TMS320DM6437 EVM Jan. 15, 2008
User guides TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (Rev. A) Dec. 18, 2007
Application notes How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) Nov. 14, 2007
Application notes Migrating from TMS320DM6446 to TMS320DM6437 Nov. 05, 2007
User guides TMS320DM643x DMP VLYNQ Port User's Guide (Rev. B) Sep. 20, 2007
User guides TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) Sep. 17, 2007
User guides TMS320DM6437 DVDP Getting Started Guide Jul. 31, 2007
Application notes TMS320DM643x Pin Multiplexing Utility Jul. 06, 2007
Application notes Migrating from TMS320DM642 to TMS320DM6437 Jun. 29, 2007
User guides TMS320C6000 Network Developer's Kit (NDK) Support Package for EVMDM6437 UG Jun. 26, 2007
User guides TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) Jun. 25, 2007
Application notes Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007
User guides TMS320DM643x DMP High-End CAN Controller (HECC) User's Guide (Rev. A) May 15, 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) Apr. 04, 2007
More literature DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) Feb. 13, 2007
More literature Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) Feb. 13, 2007
Application notes DaVinci Technology Background and Specifications (Rev. A) Jan. 04, 2007
User guides TMS320DM643x DMP 64-Bit Timer User's Guide Dec. 18, 2006
Application notes Clock Recommendations for the DM643x EVM Nov. 29, 2006
User guides TMS320C64x+ DSP Big-Endian Library Programmer's Reference Mar. 10, 2006
User guides TMS320C64x+ Image/Video Processing Library Programmer's Reference Mar. 10, 2006
Application notes Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS
TMDMFP Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Features

Multimedia Framework Products MFP


MFP is completely open source.  It is distributed under the BSD license (with the exception of kernel mode Linux drivers in the Linux Utils product, which are licensed under GPLv2), and is freely available from TI.

  • XDAIS
    TI's well-proven eXpressDSP Algorithm (...)
CODE EXAMPLES & DEMOS Download
DEMO - DM6437 Application Example & Demo Code
DEMOAPP-DM6437 Free Example Code - TI provides proof-of-concept application code to demonstrate some of the hardware and software capabilities of its devices.

  • Click GET SOFTWARE to access Application Demo and Documentation, based on the DM6437 EVM (evaluation module).
DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TI-RTOS Networking
NDKTCPIP TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for TMS320C6000(TM) High Performance DSP-based devices. 
Features

TI-RTOS Networking includes:

  • Core TCP/IP protocol stack: Dual-mode IPv6/IPv4 stack in both source and binary only including VLAN packet priority marking, TCP, UDP, ICMP, IGMP, IP, and ARP
  • Network applications: HTTP, TELNET, TFTP, DNS, DHCP (IPv4 only) in both source and binary form
  • Serial support: PPP (...)
DRIVERS & LIBRARIES Download
C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
SOFTWARE CODECS Download
CODECS - Video and Speech- C64x+-based Devices (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)
C64XPLUSCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)
Features

For best design results, find the codec(s) optimized for your platform. If none are available, click GET SOFTWARE button (above) for codecs optimized for TI C64x+ core-based devices (i.e. most devices in the OMAP35x, TMS320C645x, TMS320C647x, TMS320DM646x, TMS320DM644x and TMS320DM643x families).

  • For (...)
SOFTWARE CODECS Download
eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDM
TMDXDAISXDM xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Features
xDAIS and xDM Technical Overview eXpressDSP Digital Media (xDM) standard - The xDM standard defines APIs through which an application invokes a particular class of codec, such as video decode or audio encode. xDM APIs are defined for the following codecs classes:
  • Video decode
  • Video encode
  • Image decode
  • (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM221C.ZIP (10 KB) - BSDL Model
SIMULATION MODELS Download
SPRM222B.ZIP (10 KB) - BSDL Model
SIMULATION MODELS Download
SPRM230B.ZIP (267 KB) - IBIS Model
SIMULATION MODELS Download
SPRM231B.ZIP (267 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
BGA (ZDU) 376 View options
NFBGA (ZWT) 361 View options

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