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DaVinci Digital Media System-on-Chip

TMS320DM6443

ACTIVE

Product details

Parameters

Arm CPU 1 Arm9 Arm MHz (Max.) 297 DSP 1 C64x Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Video port (configurable) 1 Dedicated Output On-chip L2 cache/RAM 64 KB (DSP) DRAM DDR2 Ethernet MAC 10/100 USB 1 SPI 1 I2C 1 UART (SCI) 3 Rating Catalog open-in-new Find other Audio & media processors

Package | Pins | Size

NFBGA (ZWT) 361 256 mm² 16 x 16 open-in-new Find other Audio & media processors

Features

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-MHz C64x+™ Clock Rate
    • 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 16K-Byte ROM
  • Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Resize Engine Provides:
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • 4 - 54 MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-Bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
    • Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) with Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480 Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

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Description

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet TMS320DM6443 Digital Media System-on-Chip datasheet (Rev. G) Aug. 30, 2010
* Errata TMS320DM6443 Digital Media SoC Silicon Errata (Revs 2.3, 2.1, 1.3, 1.2, 1.1) (Rev. N) Aug. 12, 2010
Application note High-Speed Interface Layout Guidelines (Rev. H) Oct. 11, 2018
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug. 21, 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug. 21, 2012
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) Aug. 09, 2012
Application note Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guide TMS320DM644x DMSoC 64-bit Timer User's Guide Aug. 01, 2011
User guide TMS320C6000 Programmer's Guide (Rev. K) Jul. 11, 2011
User guide TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) Mar. 25, 2011
User guide TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) Jan. 27, 2011
User guide TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) Jan. 12, 2011
User guide TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) Dec. 23, 2010
User guide TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) Aug. 25, 2010
User guide TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) Aug. 19, 2010
Application note TMS320DM6446/3 Power Consumption Summary (Rev. B) Aug. 16, 2010
User guide TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) Aug. 06, 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) Aug. 03, 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
User guide TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) Jul. 21, 2010
Application note Migrating From TMS320DM644x v.2.1 ROM Bootloader to 2.3 Version Jul. 20, 2010
User guide TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. G) Jun. 02, 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) Mar. 18, 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) Mar. 18, 2010
Application note USB Compliance Checklist (Rev. A) Mar. 10, 2010
Application note Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) Sep. 10, 2009
Application note LSP 2.10 DaVinci Linux Drivers (Rev. A) Jul. 08, 2009
Application note Common Object File Format (COFF) Apr. 15, 2009
User guide TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) Feb. 24, 2009
User guide TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) Feb. 22, 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) Feb. 11, 2009
Application note Booting DaVinci EVM from NAND Flash (Rev. A) Dec. 15, 2008
Application note 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer Nov. 24, 2008
More literature DaVinci Technology Overview Brochure (Rev. B) Sep. 27, 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) Aug. 21, 2008
Application note Understanding the Davinci Preview Engine (Rev. A) Jul. 23, 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008
Application note Understanding the Davinci Resizer (Rev. B) Jul. 17, 2008
Application note Implementing the DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G) Jun. 16, 2008
Application note Building a Small Embedded Linux Kernel Example (Rev. A) May 27, 2008
User guide TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) May 27, 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) May 15, 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) May 15, 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) May 05, 2008
Application note TMS320DM644x Thermal Considerations (Rev. A) Apr. 23, 2008
Application note TMS320DM6441 Power Consumption Summary Application Report Apr. 08, 2008
User guide TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) Apr. 08, 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) Mar. 06, 2008
User guide TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) Feb. 25, 2008
User guide TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) Sep. 20, 2007
User guide TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) Sep. 17, 2007
Application note Running Demo via ddd on the DVEVM Jul. 30, 2007
Application note Using Static IP Between Linux Host and the DVEVM Jul. 30, 2007
Application note Compact Flash (CF) Support on the DVEVM Jul. 25, 2007
Application note Host USB Support on the DVEVM Jul. 20, 2007
Application note Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) Jun. 27, 2007
Application note Digital Video Using DaVinci SoC Jun. 27, 2007
Application note Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) Jun. 27, 2007
Application note EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) Jun. 27, 2007
User guide TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) Apr. 18, 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) Apr. 04, 2007
User guide TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide Mar. 23, 2007
User guide TMS320DM644x DVEVM Windows CE v5.0 Codec Engine Binary User's Guide Mar. 23, 2007
More literature DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) Feb. 13, 2007
More literature Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) Feb. 13, 2007
User guide TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) Feb. 07, 2007
Application note Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x Dec. 21, 2006
More literature Portable Media Player Based on DaVinci Technology Nov. 14, 2006
More literature Universal IP Player Solution from ATEME Nov. 02, 2006
Application note DaVinci System Level Benchmarking Measurements Sep. 28, 2006
More literature DaVinci Benchmarks Product Bulletin (Rev. A) Sep. 12, 2006
Application note Fast Development with DaVinci On Screen Display (OSD) Jul. 06, 2006
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference Mar. 10, 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference Mar. 10, 2006
Application note Migrating from EDMA v2.0 to EDMA v3.0 for TMS320DM644X DMSoC Dec. 03, 2005
User guide TMS320DM644x DMSoC ATA Controller User's Guide Dec. 03, 2005
User guide TMS320DM644x DMSoC DSP Subsystem Reference Guide Dec. 03, 2005
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEBUG PROBE Download
Description

TMDSADP1420 adapter – used for connecting TI and 3rd party XDS510 and XDS560-class emulators with a 14 pin native connector to the TMDXEVM6446 or customer boards with a compact (CTI) 20-pin header. The adapter improves signal integrity, translates voltages, and can optionally provide adaptive (...)

DEBUG PROBE Download
XDS200 USB Debug Probe
TMDSEMU200-U
295
Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBE Download
995
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBE Download
1495
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

SOFTWARE DEVELOPMENT KIT (SDK) Download
Linux Digital Video Software Development Kits (DVSDK) v2x/v3x - DaVinci Digital Media Processors
LINUXDVSDK-DV Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

Features

All versions of the Linux DaVinci Digital Video Software Development Kits (DVSDK) combine all the software components and tools needed to begin development of multimedia applications on DaVinci technology-based devices. 

 

DVSDK v3.10 - DM355 and DM6467T (1 GHz) – PRODUCTION
The Linux DaVinci DVSDK v3.10 (...)

APPLICATION SOFTWARE & FRAMEWORK Download
Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS
TMDMFP Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Features

Multimedia Framework Products MFP


MFP is completely open source.  It is distributed under the BSD license (with the exception of kernel mode Linux drivers in the Linux Utils product, which are licensed under GPLv2), and is freely available from TI.

  • XDAIS
    TI's well-proven eXpressDSP Algorithm (...)
DRIVER OR LIBRARY Download
C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
DRIVER OR LIBRARY Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
SOFTWARE CODEC Download
CODECS - Video and Speech- C64x+-based Devices (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)
C64XPLUSCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)
Features

For best design results, find the codec(s) optimized for your platform. If none are available, click GET SOFTWARE button (above) for codecs optimized for TI C64x+ core-based devices (i.e. most devices in the OMAP35x, TMS320C645x, TMS320C647x, TMS320DM646x, TMS320DM644x and TMS320DM643x families).

  • For (...)
SOFTWARE CODEC Download
CODECS - Optimized for DM644x Devices
DM644XCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
Features

DM644x Codecs are optimized for use on TMS320DM6441, TMS320DM6443 and TMS320DM6446 processors. For best design results, use these. If you seek additional TI codecs, find those optimized for TI C64x+ core-based devices (i.e. most devices in the OMAP35x, C645x, C647x, DM646x, DM644x and DM643x (...)

SOFTWARE CODEC Download
eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDM
TMDXDAISXDM xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Features
xDAIS and xDM Technical Overview eXpressDSP Digital Media (xDM) standard - The xDM standard defines APIs through which an application invokes a particular class of codec, such as video decode or audio encode. xDM APIs are defined for the following codecs classes:
  • Video decode
  • Video encode
  • Image decode
  • (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM199.ZIP (112 KB) - IBIS Model
SIMULATION MODEL Download
SPRM204.ZIP (10 KB) - BSDL Model
SIMULATION MODEL Download
SPRM326A.ZIP (8 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
NFBGA (ZWT) 361 View options

Ordering & quality

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  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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