Product details

DSP 3 C64x+ DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) -40 to 100, -40 to 95, 0 to 85
DSP 3 C64x+ DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) -40 to 100, -40 to 95, 0 to 85
  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

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Technical documentation

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Type Title Date
* Data sheet TMS320C6474 Multicore Digital Signal Processor Data Manual datasheet (Rev. H) 11 Apr 2011
* Errata TMS320C6474 DSP Silicon Errata (Silicon Revisions 2.1, 1.3, 1.2) (Rev. C) 11 Mar 2011
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) 19 May 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 19 Jul 2013
More literature Picture it: DSPs in medical imaging (Rev. C) 12 Jul 2013
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide TMS320C6474 DSP EMAC/MDIO Module Reference Guide (Rev. B) 02 Mar 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B) 01 Jul 2011
User guide Bootloader User's Guide for the TMS320C645x/C647x DSP (Rev. G) 03 Jun 2011
User guide TMS320C6474 DSP DDR2 Memory Controller User's Guide (Rev. D) 02 Jun 2011
Application note Tuning VCP2 and TCP2 Bit Error Rate Performance 11 Feb 2011
User guide TMS320C6474 Serial RapidIO (SRIO) User's Guide (Rev. D) 03 Feb 2011
Application note TMS320C6474 Hardware Design Guide (Rev. B) 03 Aug 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
User guide TMS320C6474 DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. A) 18 May 2010
User guide TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference Guide (Rev. B) 08 Dec 2009
User guide TMS320C6474 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A) 28 Oct 2009
Application note Connecting Antenna Interface (AIF) With TDM Bridge Chip (IDT 80HFC001) 28 Aug 2009
Application note Direct I/O Library 28 Aug 2009
Application note Using the TMS320C6474 Antenna Interface (AIF) for Inter-DSP Communication 28 Aug 2009
Application note TMS320C6474 DDR2 Implementation Guidelines (Rev. A) 04 Aug 2009
Application note How to Approach Inter-Core Communication on TMS320C6474 27 Jan 2009
Application note Inter-Core Communication on TMS320C6474 12 Jan 2009
Application note TPS40197 Reference Design 17 Dec 2008
White paper See the difference:DSPs in medical imaging 31 Oct 2008
Application note Migrating from TMS320C6455 to TMS320C6474 14 Oct 2008
Application note TMS320C6474 Power Consumption Summary 14 Oct 2008
User guide TMS320C6474 Antenna Interface User's Guide 14 Oct 2008
Application note TMS320C6474 Common Bus Architecture (CBA) Throughput 14 Oct 2008
User guide TMS320C6474 DSP 64-Bit Timer User's Guide 14 Oct 2008
User guide TMS320C6474 DSP Chip Interrupt Controller (CIC) User's Guide 14 Oct 2008
User guide TMS320C6474 DSP General-Purpose Input/Output (GPIO) User's Guide 14 Oct 2008
User guide TMS320C6474 DSP Power/Sleep Controller (PSC) User’s Guide 14 Oct 2008
User guide TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG 14 Oct 2008
User guide TMS320C6474 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide 14 Oct 2008
User guide TMS320C6474 Frame Synchronization User's Guide 14 Oct 2008
Application note TMS320C6474 Module Throughput Application Report 14 Oct 2008
Application note TMS320C6474 Multicore Digital Signal Processor Technical Brief 14 Oct 2008
Application note TMS320C6474 SERDES Implementation Guidelines 14 Oct 2008
User guide TMS320C6474 Semaphore User's Guide 14 Oct 2008
Application note C6474 (x4) Power Using Modules 01 Oct 2008
Application note C6474 (x2) Power Using Modules 30 Sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Oct 2005
User guide High-Speed DSP Systems Design Reference Guide 20 May 2005

Design & development

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Debug probe

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Debug probe

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

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Software development kit (SDK)

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Software development kit (SDK)

C6474SWPKG — TMS320C6474 Software

AET Target Library for 64x/64x+ - Advanced Event Triggering that allows programming of AET from target code.

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Software development kit (SDK)

S2MEDDUS — Medical Imaging Software Tool Kits (STK)

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Driver or library

NDKTCPIP — TI-RTOS Networking

TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for high-performance TMS320C6000™ DSP-based devices.
Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support (RTS) Library

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SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

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Driver or library

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Driver or library

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IDE, configuration, compiler or debugger

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Software codec

C64XPLUSCODECS — CODECS - Video and Speech- C64x+-based Devices (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

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Software codec

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Software codec

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Software codec

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Simulation model

C6474 ZUN BSDL Model

SPRM335.ZIP (7 KB) - BSDL Model
Simulation model

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Design tool

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