Product details


Number of supplies monitored 32 VCC (Min) (V) 3.15 VCC (Max) (V) 3.63 Iq (Typ) (uA) 31400 Time delay (ms) Programmable Number of sequenced outputs 32 Rating Catalog open-in-new Find other Sequencers

Package | Pins | Size

NFBGA (ZWS) 169 144 mm² 12 x 12 open-in-new Find other Sequencers


  • Sequence, monitor, and margin 24 voltage rails plus 8 digital rails
  • Monitor and respond to OV, UV, OC, UC, temperature, time-out, and GPI-triggered faults
  • Flexible sequence-on and off dependencies, delay time, Boolean logic, and GPIO configuration to support complex sequencing aplications
  • Four rail profiles for adaptive voltage identification (AVID) voltage regulator
  • High-accuracy closed-loop margining
  • Active trim function improves rail output voltage accuracy
  • Advanced nonvolatile event logging to assist system debugging
    • Single-event fault log (100 entries)
    • Peak value log
    • Black box fault log to save status of all rails and I/O pins at the first fault
  • Easily cascade up to 4 power sequencers and take coordinated fault responses
  • Programmable watchdog timer and system reset
  • Pin-selected rail state
  • PMBus™ 1.2 compliant
  • Dual-bank configurations to provide a fail-safe state when programming

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The UCD90320 device is a 32-rail PMBus™ addressable power sequencer and system manager in a compact 0.8-mm pitch BGA package.

The 24 integrated ADC channels (AMONx) monitor the power supply voltage, current, and temperature. Of the 84 GPIO pins, 8 can be used as digital monitors (DMONx), 32 to enable the power supply (ENx), 24 for margining (MARx), 16 for logical GPO, and 32 GPIs for cascading, and system function.

The 32 ENx pins and the 16 LGPOx pins can be configured to be active driven or open drain outputs.

Nonvolatile event logging preserves fault events after power dropout. Black box fault log feature preserves the status for all rails and I/O pins when the first fault occurs. The cascading feature offers convenient ways to manage up to 128 voltage rails through one SYNC_CLK pin connection.

The FAULT pin coordinates the cascaded devices to take synchronized fault responses. The pin-selected rail states feature uses up to 3 GPIs to control up to eight user-defined power states. These states can implement system low-power modes as outlined in the Advanced Configuration and Power Interface (ACPI) specification.

The TI Fusion Digital Power™ designer software is an intuitive PC-based graphic user interface (GUI) that can configure, store, and monitor all system operating parameters.

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Technical documentation

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Type Title Date
* Datasheet UCD90320 32-Rail PMBus Power Sequencer and System Manager datasheet (Rev. C) Mar. 11, 2020
User guide UCD90320 Sequencer and System Health Controller PMBus Command Reference (Rev. C) Feb. 26, 2020
Application note How to Decode UCD90xxx Fault Log With PMBus (Rev. A) Nov. 07, 2019
Application note Improvements to the UCD90320 Device Jul. 01, 2019
Application note Design Voltage Margining Circuit for UCD90xxx Power Sequencer and System Manager (Rev. A) May 21, 2019
Application note UCD90xxx Family Frequently Asked Questions and Answers (Rev. B) Apr. 12, 2019
User guide UCD90xxx Sequencer Schematics Guidelines (Rev. C) Mar. 24, 2019
User guide UCD90320 Sequencer and System Health Controller PMBus Command Reference (Rev. B) Jun. 20, 2018
Application note How to Cascade Multiple UCD90xxx Sequencers Aug. 10, 2017
User guide Fusion Digital Power Designer GUI 7.0 for the UCD90xxx Sequencer May 31, 2017
Technical article Sequencing and managing multiple power rails in a system: common questions answered Feb. 01, 2017
Technical article Reducing solution size with PMBus in multi-rail systems Nov. 04, 2016
User guide UCD90320EVM-783 32-Rail Sequencer Development Board Jul. 28, 2016
Application note Power-supply sequencing for FPGAs Oct. 24, 2014
Application note Monitoring Voltage, Current and Temperature Using the UCD9012x Mar. 23, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The UCD90320EVM-783 is designed for the evaluation of the UCD90320, a 32-rail PMBus power sequencer and system manager. Access to all of the I/O pins is provided via strip connectors for integration into complex systems using jumper wires. The UCD90320EVM provides a PMBus (power management bus (...)

  • Powered by single 5-V supply
  • Status LEDs on all digital I/O pins
  • 16 pull-up and 16 pull-down pins to configure GPI inputs or open-drain GPO output
  • 84 LEDs to monitor GPIO, Logic GPO, EN, DMON and MAR inputs and outputs
  • Strip connector I/O access
  • On-board TPS54678 and TPS7A84 LDO power stages for (...)

This EVM serves as an interface adapter or a bridge between a host PC (IBM™ compatible) and one or multiple slave devices via a standard type-A to mini-B USB cable. The communication between the USB interface adapter and the host PC is via USB, while the communication between the USB interface (...)

  • Supports master mode I²C, SMBus or PMBus as well as GPIO.
  • Supports USB1.1 full speed at 12 Mbit/s. The USB interface adapter is recognized by the host as a generic human interface device (HID), so no proprietary USB or HID driver is needed. Therefore, the USB interface adapter can be treated as a (...)

Software development

Digital Power Software
FUSION_DIGITAL_POWER_DESIGNER Fusion Digital Power™  is the Graphical User Interface (GUI) used to configure and monitor select Texas Instruments digital power controllers and sequencer/health monitors. The application uses the PMBus protocol to communicate with the device over serial bus by way of a TI USB adapter.

Some of the tasks you can perform with the GUI include:

  • Turn on or off the power supply output, either through the hardware control line or the PMBus OPERATION command
  • Monitor real-time data. Items such as input voltage, output voltage, output current, temperature, and warnings/faults are continuously (...)

Design tools & simulation

SLUM618.ZIP (5 KB) - BSDL Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SLVC676.ZIP (88 KB)

CAD/CAE symbols

Package Pins Download
NFBGA (ZWS) 169 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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