ADC12DJ3200QML-SP

ACTIVO

Radiation-hardened, QML-V, 300krad, 12 bit, dual 3.2GSPS or single 6.4GSPS ADC

Detalles del producto

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² (15 mm × 15 mm)
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

Descargar Ver vídeo con transcripción Video

Documentación técnica

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 10
Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) PDF | HTML 21/03/2025
* Informe de radiación y confiabilidad ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 3/08/2020
* Informe de radiación y confiabilidad Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 4/05/2012
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 4/08/2020
Guía de selección TI Space Products (Rev. L) 27/03/2026
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17/06/2025
Nota sobre la aplicación Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10/06/2025
Más documentación TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20/02/2025
Nota sobre la aplicación Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19/10/2022
Artículo técnico How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 17/10/2022

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC12DJ3200EVMCVAL — Módulo de evaluación ADC12DJ3200QML-SP

El módulo de evaluación (EVM) ADC12DJ3200 está diseñado para evaluar los convertidores analógico a digital (ADC) de alta velocidad ADC12DJ3200QML-SP. El EVM está equipado con el ADC12DJ3200QML-SP, un ADC de calidad espacial de 12 bits, 4 GSPS de doble canal o 8 GSPS de un solo canal con interfaz (...)
Guía del usuario: PDF
Productos y hardware compatibles
En inventario
Límite:
??asset.out-of-stock-ti_es_MX??
No disponible
Firmware

TI204C-IP — Request for JESD204 rapid design IP

La IP de diseño rápido JESD204 se diseñó para permitir a los ingenieros de FPGA lograr una ruta acelerada hacia un sistema JESD204 en funcionamiento. La IP se diseñó de manera que el procesamiento digital descendente y otras lógicas de aplicación estén aislados de la mayoría de las restricciones (...)

Productos y hardware compatibles
Soporte de software

SLVC806 — Xilinx AlphaData Demo

Productos y hardware compatibles
Modelo de simulación

ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

SLVMDV3.ZIP (47828 KB) - Modelo IBIS-AMI
Productos y hardware compatibles
Modelo de simulación

ADC12DJ3200QML-SP S-Parameter Model

SLVMDU7.ZIP (9 KB) - Modelo de parámetros-S
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CCGA-FC (NWE) 196 Ultra Librarian

Pedidos y calidad

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene alguna pregunta sobre calidad, encapsulados o pedido de productos de TI, consulte el servicio de asistencia de TI. ​​​​​​​​​​​​​​

Videos