Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC12DJ3200QML-SP

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Protección contra la radiación garantizada (RHA), QMLV, 300 krad, 12 bits, ADC 3.2 GSPS doble o ADC

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ADC12DJ3200QML-SP

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Detalles del producto

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (bit) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (bit) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² 15 x 15 CLGA-FC (ZMX) 196 225 mm² 15 x 15
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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Documentación técnica

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Tipo Título Fecha
* Data sheet ADC12DJ3200QML-SP 6.4-GSPS, Single-Channel or 3.2-GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 24 mar 2021
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 04 ago 2020
* Radiation & reliability report ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 03 ago 2020
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 04 may 2012
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 ago 2023
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 nov 2022
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 oct 2022
Technical article How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 17 oct 2022
Selection guide TI Space Products (Rev. I) 03 mar 2022
EVM User's guide ADC12DJ3200EVMCVAL Evaluation Module User's Guide 11 ene 2018

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC12DJ3200EVM — Módulo de evaluación de ADC de muestreo de RF ADC12DJ3200 de 12 bits, 3,2 GSPS dobles o 6,4 GSPS sim

The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)

Guía del usuario: PDF
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Placa de evaluación

ADC12DJ3200EVMCVAL — Módulo de evaluación ADC12DJ3200QML-SP

El ADC12DJ3200EVMCVAL consiste en un módulo de evaluación (EVM) que tiene como función evaluar el dispositivo ADC12DJ3200QML-SP. El ADC12DJ3200QML-SP es un convertidor de señal analógica a digital (ADC) de muestreo de RF de calidad espacial, baja potencia, 12 bits, doble de 3.2 GSPS o simple de (...)

Guía del usuario: PDF
No disponible en TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP para FPGA conectadas a convertidores de datos de alta velocidad TI

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Soporte de software

SLVC806 — Xilinx AlphaData Demo

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Productos y hardware compatibles

Productos y hardware compatibles

Productos
ADC de alta velocidad (≥ 10 MSPS)
ADC12DJ3200QML-SP — Protección contra la radiación garantizada (RHA), QMLV, 300 krad, 12 bits, ADC 3.2 GSPS doble o ADC
Desarrollo de hardware
Placa de evaluación
ADC12DJ3200EVMCVAL — Módulo de evaluación ADC12DJ3200QML-SP
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Modelo de simulación

ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

SLVMDV3.ZIP (47828 KB) - IBIS-AMI Model
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Modelo de simulación

ADC12DJ3200QML-SP S-Parameter Model

SLVMDU7.ZIP (9 KB) - S-Parameter Model
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Plano de montaje

ADC12DJ3200QML-EVM Assembly Package

SLVRBF5.ZIP (4838 KB)
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Archivo Gerber

ADC12DJ3200EVMCVAL Design Files

SLVC819.ZIP (4838 KB)
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Paquete Pasadores Descargar
CCGA-FC (NWE) 196 Ver opciones
CLGA-FC (ZMX) 196 Ver opciones
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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