Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC12J2700

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Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits y 2,7 GSPS

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ADC12J2700

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Detalles del producto

Sample rate (max) (Msps) 2700 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.725 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 55.1 ENOB (Bits) 8.8 SFDR (dB) 72 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 2700 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.725 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 55.1 ENOB (Bits) 8.8 SFDR (dB) 72 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (NKE) 68 100 mm² 10 x 10
  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Usable Output Bandwidth of 540 MHz at
    4x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 320 MHz at
    4x Decimation and 1600 MSPS
  • Usable Output Bandwidth of 67.5 MHz at
    32x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 40 MHz at
    32x Decimation and 1600 MSPS
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 1600 or 2700 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: –147.3 dBFS/Hz (ADC12J2700)
    • Noise Floor: –145 dBFS/Hz (ADC12J1600)
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (2700 MSPS): 1.8 W
      • Bypass (1600 MSPS): 1.6 W
      • Power Down Mode: <50 mW
  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Usable Output Bandwidth of 540 MHz at
    4x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 320 MHz at
    4x Decimation and 1600 MSPS
  • Usable Output Bandwidth of 67.5 MHz at
    32x Decimation and 2700 MSPS
  • Usable Output Bandwidth of 40 MHz at
    32x Decimation and 1600 MSPS
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 1600 or 2700 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: –147.3 dBFS/Hz (ADC12J2700)
    • Noise Floor: –145 dBFS/Hz (ADC12J1600)
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (2700 MSPS): 1.8 W
      • Bypass (1600 MSPS): 1.6 W
      • Power Down Mode: <50 mW

The ADC12J1600 and ADC12J2700 devices are wideband sampling and digital tuning devices. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J1600 and ADC12J2700 devices are available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

The ADC12J1600 and ADC12J2700 devices are wideband sampling and digital tuning devices. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J1600 and ADC12J2700 devices are available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet ADC12Jxx00 12-Bit 1.6- or 2.7-GSPS ADCs With Integrated DDC datasheet (Rev. D) PDF | HTML 19 oct 2017
Technical article Beyond the first Nyquist zone PDF | HTML 25 sep 2015
Application note System solution for avionics & defense 23 sep 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 mar 2015

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC12J2700EVM — Módulo de evaluación del convertidor analógico a digital de muestreo de RF ADC12J2700 de 12 bits, 2,

The ADC12J2700EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADC12J2700. The ADC12J2700 is a low power, 12-bit, 2.7-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and (...)

Guía del usuario: PDF
No disponible en TI.com
Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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GUI para el módulo de evaluación (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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Modelo de simulación

ADC12J1600 IBIS Model (Rev. A)

SLAM223A.ZIP (24 KB) - IBIS Model
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Modelo de simulación

ADC12J4000 IBIS-AMI Model (Rev. A)

SLAM198A.ZIP (4134 KB) - IBIS-AMI Model
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Herramienta de cálculo

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

Productos y hardware compatibles

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)
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Diseños de referencia

TIDA-00432 — Sincronización de ADC de JESD204B Giga-Sample mediante la plataforma Xilinx para sistemas de radar d

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
VQFNP (NKE) 68 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL)/reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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