ADS61JB23

ACTIVO

Convertidor analógico a digital (ADC) de 12 bits y 80 MSPS

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet (Inglés)

ADS61JB23

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

440

Architecture

Pipeline

SNR (dB)

71.7

ENOB (Bits)

11.5

SFDR (dB)

80

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

440

Architecture

Pipeline

SNR (dB)

71.7

ENOB (Bits)

11.5

SFDR (dB)

80

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate of 1.6 Gbps
- Meets JESD204A Specification
- CML Outputs with Current Programmable from 2 mA – 32 mA
Power Dissipation:
- 440 mW at 80 MSPS in Single Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
71.7 dBFS SNR at 70 MHz IF
Analog Input FSR: 2 Vpp
External and Internal (trimmed) Reference Support
1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
Programmable Digital Gain: 0dB – 6dB
Straight Offset Binary or Twos Complement Output
Package:
- 6 mm × 6 mm QFN-40

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate of 1.6 Gbps
- Meets JESD204A Specification
- CML Outputs with Current Programmable from 2 mA – 32 mA
Power Dissipation:
- 440 mW at 80 MSPS in Single Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
71.7 dBFS SNR at 70 MHz IF
Analog Input FSR: 2 Vpp
External and Internal (trimmed) Reference Support
1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
Programmable Digital Gain: 0dB – 6dB
Straight Offset Binary or Twos Complement Output
Package:
- 6 mm × 6 mm QFN-40

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

filter

Buscar otro/a ADC de alta velocidad (≥ 10 MSPS)

Descargar Ver vídeo con transcripción Video

Documentación técnica

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.

Ver todo 3

Documentación principal	Tipo	Título	Fecha
*	Hoja de datos	12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet	1/12/2012
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19/07/2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Firmware

TI204C-IP — Request for JESD204 rapid design IP

La IP de diseño rápido JESD204 se diseñó para permitir a los ingenieros de FPGA lograr una ruta acelerada hacia un sistema JESD204 en funcionamiento. La IP se diseñó de manera que el procesamiento digital descendente y otras lógicas de aplicación estén aislados de la mayoría de las restricciones (...)