Good PCB design and layout can be extremely effective in suppressing ESD in the system. These are general guidelines for ESD- and EMI-immune PCB layout:

• Use ground planes instead of ground traces where possible to lower the current-path inductance.
• Use multipoint and thicker grounds where you want ESD currents to flow, and single-point and thinner grounds where you don't.
• If it is not practicable to create a continuous ground plane by using copper pour in the layout, then create smaller copper pour sections that are in turn connected to the rest of the ground. However, do not create isolated copper pour islands; they can induce noise and arc in presence of ESD.
• If possible, use multi-layer PCBs with paired power and ground planes.
• If possible, place solid or filled vias into power and ground planes. These vias provide excellent thermal dissipation in case of an ESD event and also ensure good electrical and power supply connections. For the plated through-hole components, use thermal vias.
• Keep traces as short as possible to reduce trace inductance.
• Avoid routing traces at right angles to component pins or other traces. Right angle traces should be avoided as they are known to cause more radiation. This becomes more critical in high-speed designs.
  Figure 2-5 Avoid Right-Angle Traces
• Keep sensitive signal traces away from PCB edges.
• Place all connectors and external wires on one edge of the PCB.
• Place ESD susceptible circuitry at the center of the PCB (away from the edges of the board, external wires, connectors and power).
• Decoupling (see Figure 2-6)
  • Use decoupling capacitors with low effective series resistance (ESR) and effective series inductance (ESL) to decouple the IC (MSP430 in this case) power from the rest of the supply system.
  • Place the decoupling capacitor close to the IC power pins.
  • Keep the traces from decoupling caps to GND as short (and thick) as possible.
  Figure 2-6 Decoupling Basics
• Crystal layout

  Crystal connections on PCB layout are very important as crystals are susceptible to ESD and EMI noise in the system. Poor designs can cause the crystal to dropout or cause jitter in the crystal oscillator clock. These are general guidelines for ESD-immune PCB layout practices:

  • Crystal should be placed as close to the MSP430 as possible
  • The traces connecting the crystal should be short and direct
  • Ensure no traces run beneath the crystal
  • Keep switching signals away from the crystal layout to avoid causing crystal dropout (see Section 5 for real world example based on this)
  • Keep a clean ground plane beneath the crystal
  • Ground the crystal can as well; use guard rings around the leads

  Figure 2-7 shows an example crystal layout that follows all of these design recommendations.

  Figure 2-7 Example Crystal Layout

  This topic is discussed in greater detail in the MSP430 32-kHz Crystal Oscillator application note) [11].

• Current Loops

  An electrical circuit is always a closed loop. Every signal path has a return path back to the source; also called the return current. With DC, the return current takes the lowest resistance path back. With higher frequency, the return current flows along the lowest impedance; that is directly beneath the forward signal path [12]. Current loops in the layout generate noise and should be minimized by keeping forward and return currents together. It helps both EMI and ESD performance. Solid ground plane provides continuous, low-impedance path for return current.

  • For a two-layer board, try to dedicate one layer as mostly solid ground plane, with routing slots cut out for signal traces
  • Figure 2-8 shows a solid ground plane. Only breaks in the plane are vias and through-holes. This is the ideal case.
    Figure 2-8 Example Layout With Solid Ground Plane
  • If one of the layers cannot be dedicated as ground plane, then use a star configuration instead of a daisy chain configuration to connect all grounds. Daisy chaining forces all the signals to follow the same return path possibly causing ground bounce.
    Figure 2-9 Grounding Considerations For 2-Layer Board With No Dedicated Ground Plane
  • Make sure that no traces on the other layer perpendicularly cross a break or slot in the ground plane. Otherwise, it forms a large inductive loop that can generate and pick up noise. If the return path, particularly the ground plane, has a break or slot, the return current must take a different route, and this results in a loop area (see Figure 2-10(a)). The larger the loop area, the more radiation and EMI problems occur.
    Figure 2-10 Return Currents and Resulting Loop Area
  • The designer must make sure that the return current flows directly underneath the signal trace. One way is to physically connect the areas separated by the slot (for example, by placing a 0-Ω resistor over the slot) Figure 2-10(b). Another way is to route the signal same way as the return current flows Figure 2-10(c) [12]. This is also the best way here.
  • Keep loop areas between power and ground as small as possible (see Section 2.2.1 for example layout discussion illustrating this).
  • Keep loop areas of switching signals as small as possible.
  • Keep loop area of oscillator signals as small as possible.