|
| SC_OCD2_FAULT_DLY1_7 (Bit 7): bit 7 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_6 (Bit 6): bit 6 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_5 (Bit 5): bit 5 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_4 (Bit 4): bit 4 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_3 (Bit 3): bit 3 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_2 (Bit 2): bit 2 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_1 (Bit 1): bit 1 of the OCD2_FAULT
delay 1 |
| SC_OCD2_FAULT_DLY1_0 (Bit 0): bit 0 of the OCD2_FAULT
delay 1 |
|
| DLY2 has to be
written first and then DLY1. Delay is (OCD2_FAULT_DLY2 * 256 +
OCD2_FAULT_DLY1 + 1) * 0.187ms + 0.0625ms. 0x000 is disabled, 0x001
is 0.4365ms, 0x002 is 0.6235ms, 0x003 is 0.8105ms, .., 0x1fff is
1531.9665ms. |