Product details


Regulated outputs (#) 13 Vin (Min) (V) 5.6 Vin (Max) (V) 21 Iout (Max) (A) 21, 25 Step-down DC/DC controller 3 Step-down DC/DC converter 3 Step-up DC/DC controller 0 Step-up DC/DC converter 0 LDO 4 Iq (Typ) (mA) 0.3 Features Comm Control, Dynamic Voltage Scaling, Enable, Enable Pin, I2C Control, Over Current Protection, Power Good, Power Sequencing, Synchronous Rectification, Thermal Shutdown, UVLO Fixed Operating temperature range (C) -40 to 85 Rating Catalog Processor name X86, ARM, FPGA, Zynq UltraScale+, Artix-7 Processor supplier Xilinx, Altera Shutdown current (Typ) (uA) 65 Configurability Factory programmable, Software configurable open-in-new Find other Multi-channel ICs (PMIC)

Package | Pins | Size

VQFN (RSK) 64 64 mm² 8 x 8 open-in-new Find other Multi-channel ICs (PMIC)


  • Wide VIN Range From 5.6V to 21 V
  • Three Variable-Output Voltage Synchronous
    Step-Down Controllers With DCAP2™ Topology
    • Scalable Output Current Using External FETs
      With Selectable Current Limit
    • I2C DVS Control From 0.41 V to 1.67 V in
      10-mV Steps or 1 V to 3.575 V in 25-mV Steps
  • Three Variable-Output Voltage Synchronous Step-Down
    Converters With DCS-Control Topology
    • VIN Range From 4.5 V to 5.5 V
    • Up to 3 A of Output Current
    • I2C DVS Control From 0.41 V to 1.67 V
      in 10-mV Steps or 0.425 V to 3.575 V in 25-mV
  • Three LDO Regulators With Adjustable Output Voltage
    • LDOA1: I2C-Selectable Output Voltage
      From 1.35 V to 3.3 V for up to 200 mA of Output
    • LDOA2 and LDOA3: I2C-Selectable Output
      Voltage From 0.7 V to 1.5 V for up to 600 mA of
      Output Current
  • VTT LDO for DDR Memory Termination
  • Three Load Switches With Slew Rate Control
    • Up to 300 mA of Output Current With Voltage
      Drop Less Than 1.5% of Nominal Input Voltage
    • RDSON < 96 mΩ at Input Voltage
      of 1.8 V
  • 5-V Fixed-Output Voltage LDO (LDO5)
    • Power Supply for Gate Drivers of SMPS and
      for LDOA1
    • Automatic Switch to External 5-V Buck for Higher
  • Built-in Flexibility and Configurability by Factory
    OTP Programming
    • Six GPI Pins Configurable to Enable (CTL1 to CTL6)
      or Sleep Mode Entry (CTL3 and CTL6) of Any Selected
    • Four GPO Pins Configurable to Power Good of Any
      Selected Rails
    • Open-Drain Interrupt Output Pin
  • I2C Interface Supports:
    • Standard Mode (100 kHz)
    • Fast Mode (400 kHz)
    • Fast Mode Plus (1 MHz)
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The TPS650860 device is a single-chip power-management IC designed for multicore processors, FPGAs, and other System-on-Chips (SoCs). The TPS650860 offers an input range of 5.6 V to 21 V, enabling a wide range of applications. The device is well suited for NVDC and non-NVDC power architecture using 2S, 3S, or 4S Li-Ion battery packs. See the Application Section for 5-V input supplies. The D-CAP2 and DCS-Control high-frequency voltage regulators use small inductors and capacitors to achieve a small solution size. The D-CAP2 and DCS-Control topologies have excellent transient response performance, which is great for processor core and system memory rails that have fast load switching. An I2C interface allows simple control either by an embedded controller (EC) or by an SoC. The PMIC comes in an 8-mm × 8-mm, single-row VQFN package with thermal pad for good thermal dissipation and ease of board routing.

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Technical documentation

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Type Title Date
* Data sheet TPS650860 Configurable Multirail PMU for Multicore Processors datasheet (Rev. A) Dec. 10, 2015
Application note Optimizing Resistor Dividers at a Comparator (Rev. B) Apr. 30, 2021
Application note How to Design Flexible Processor Power Systems Using PMICs (Rev. B) Jan. 27, 2020
User guide TPS650860 PMIC User's Guide For I2C Configurable-Systems Jan. 18, 2018
Application note Push-Button Circuit (Rev. B) Nov. 01, 2017
White paper Simple power rail sequencing solutions for complex multi-rail systems Jul. 06, 2016
Technical article Eliminate multistage architecture and improve industrial PC system efficiency Apr. 22, 2016
Application note TPS65086x Schematic and Layout Checklist (Rev. A) Dec. 02, 2015
User guide TPS65086x Design Guide Nov. 19, 2015
More literature TPS650860 PMIC Product Bulletin Sep. 28, 2015
Application note Basic Calculation of a Buck Converter's Power Stage (Rev. B) Aug. 17, 2015
White paper Power management integrated buck controllers for distant point-of-load apps Aug. 14, 2015
Application note Advantages of the Highly-Programmable DC/DC Controllers in the TPS65086x PMIC Mar. 27, 2015
Application note Controlling switch-node ringing in synchronous buck converters Apr. 26, 2012
Application note Ringing Reduction Techniques for NexFET High Performance MOSFETs Nov. 16, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

TPS650860 Evaluation Module
document-generic User guide

Evaluation Module (EVM) for the TPS65086x family. The EVM provides a platform for engineers to evaluate, test, and explore the TPS650860 in a real world application use. All of the sequencing and functionality required for the processor and system is demonstrated on this board. This EVM also (...)

  • DVS
  • Sequencing
  • I2C Communication and Controls
  • Holistic System Example Architecture
  • This circuit design is tested and orderable and includes GUI and User's Guide

Software development

Linux Driver for TPS65086
TPS65086SW-LINUX The Linux driver supports the TPS65086 Power Management IC. The Linux driver supports communication through the I2C bus and interfaces with the Regulator sub-system.


Linux Mainline Status

Available in Linux Main line: Yes
Available through N/A

Supported Devices:

  • tps65086


Linux Source Files

The (...)

IPG-UI The IPG-UI GUI can be used to configure multiple PMIC devices to evaluate the features and performance of those devices.  This GUI is build using web based technologies and supports interacting with the EVM hardware using a USB2ANY adapter board. The USB2ANY Explorer is provided to allow (...)
SWCC016.ZIP (15862 KB)

Design tools & simulation

SWCM006.ZIP (37 KB) - IBIS Model
SWCM007.ZIP (26 KB) - IBIS Model
SWCM008.ZIP (0 KB) - Thermal Model

Reference designs

Reference Design for Powering a Xilinx Zynq UltraScale+ Remote Radio Head (RRH) or Backhaul (BH)
PMP12004-HE — This design for powering Xilinx Zynq UltraScale+ ( Remote Radio Heads (RRH) features the TPS6508640 and is a small and highly efficient solution. The PMIC reduces size, cost, and power loss by having integrated rails into 1 device, high switching frequency and separate rails for (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RSK) 64 View options

Ordering & quality

Information included:
  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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