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線性與低壓差 (LDO) 穩壓器

TPS7A53

現行

3-A、低輸入電壓 (1.1 V) 低雜訊高準確度超低壓差 (LDO) 電壓穩壓器

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產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
具備升級功能，可直接投入使用替代所比較的裝置。
TPS7A53B 現行 具有 0.5-V 低 VREF 的 3-A、1.1-V、低 VIN、低雜訊高準確度、超低壓降電壓穩壓器 Wider output voltage range, down to 0.5V
功能相同，但針腳輸出與所比較的裝置不同。
TPS7A84A 現行 具有電源良好功能的 3-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差電壓穩壓器 Low noise 3-A LDO with ANY-OUT programming.
TPS7A53-Q1 現行 車用、3-A、低 VIN (1.1 V) 低雜訊高準確度超低壓差 (LDO) 電壓穩壓器 Low noise 3-A LDO with an extended temperature range.

TPS7A53

現行
產品規格表 立即訂購

產品詳細資料

Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 3 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 35 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 60 Operating temperature range (°C) -40 to 125
Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 3 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 35 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 60 Operating temperature range (°C) -40 to 125
VQFN-HR (RPS) 12 5.5 mm² (2.5 mm × 2.2 mm)
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 110 mV (max) at 3 A with BIAS
  • Power-supply rejection ratio:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 110 mV (max) at 3 A with BIAS
  • Power-supply rejection ratio:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package

The TPS7A53 is a low-noise (4.4 µVRMS), ultra-low dropout linear-regulator (LDO) capable of sourcing 3 A with only 110 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A53 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and
5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A53 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A53 that makes the device a component of choice for analog loads such as VCO, ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.

The TPS7A53 is a low-noise (4.4 µVRMS), ultra-low dropout linear-regulator (LDO) capable of sourcing 3 A with only 110 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A53 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and
5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A53 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A53 that makes the device a component of choice for analog loads such as VCO, ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS7A53 3-A, High-Accuracy (0.5%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator datasheet (Rev. B) PDF | HTML 2020/5/7
白皮書 Demystifying LDO Turn-On (Start-Up) Time (Rev. B) PDF | HTML 2026/3/10
白皮書 Reduce System Noise Using Parallel LDOs PDF | HTML 2025/11/3
白皮書 Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022/12/14
白皮書 Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022/12/13
應用說明 Point-of-Load Solutions for Network Interface Cards (NIC) PDF | HTML 2021/9/8
技術文章 Minimize noise and ripple with a low-noise buck converter PDF | HTML 2020/10/21

設計與開發

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開發板

TPS7A53EVM-031 — 適用於 3-A、低 VIN、低雜訊、高精確度超 LDO 電壓穩壓器的 TPS7A53 評估模組

TPS7A53 評估模組 (EVM) 爲典型配置設計，用於評估 TPS7A53 裝置的運作和性能，TPS7A54 是一款高準確度、3-A、低 VIN、低-VOUT、低壓差 (LDO) 電壓穩壓器。

EVM 電路板主要配置爲參考設計，可供需要高達 3 A 動態負載電流的工程應用。

使用指南: PDF | HTML
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模擬型號

TPS7A5201RPS PSpice Model (Rev. A)

SBVM952A.ZIP (3263 KB) - PSpice 模型
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模擬型號

TPS7A5301RPS PSpice Model

SBVM954.ZIP (19 KB) - PSpice 模型
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計算工具

PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator

並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。

在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。

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參考設計

TIDA-010230 — 適用雷達和 EW 應用的多通道射頻收發器、低雜訊時脈參考設計

在現代雷達和電子作戰 (EW) 系統中，有源電子掃描陣列 (AESA) 天線系統通常會搭配高速多通道 RF 收發器使用。這些系統需要能進行精確通道間偏斜調整的超低雜訊時脈，以獲得最佳系統性能，例如訊噪比 (SNR)、無雜散動態範圍 (SFDR)、IMD3 和有效位元數 (ENOB)。此參考設計展示了 LMX2820 和 LMK04832 架構的低雜訊 JESD204B 相容時脈，可為多個 AFE7950 提供最高 X 頻段的操作的並同步成 < 10 ps，此外可於 9-GSPS/3-GSPS DAC/ADC 時脈提高系統性能。
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VQFN-HR (RPS) 12 Ultra Librarian
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