12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)


Models (2)

Title Category Type Size (KB) Date Views
ADC12DJ3200 IBIS-AMI Model IBIS-AMI Model ZIP 5569 KB 28 Jun 2017 0 views
ADC12DJ3200 IBIS Model IBIS Model ZIP 36 KB 26 May 2017 0 views

Design kits & evaluation modules (1)

Name Part# Type
ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module ADC12DJ3200EVM Evaluation Modules & Boards

Reference designs

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TI Designs

High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)

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Software (3)

ADC12DJxx00 GUI (Rev. A)  (ZIP 177821 KB )    16 Jan 2018  
Xilinx KCU105 + ADC12DJ3200 JMODE0/JMODE2 Design Firmware  (ZIP 67948 KB )    30 Aug 2017  
Arria10 + ADC12DJ3200 JMODE0 Design Firmware  (ZIP 9527 KB )    25 May 2017  

Development tools (1)

Name Part# Type
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator FREQ-DDC-FILTER-CALC Calculation Tools