SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The device contains an additional PIE vector table, in addition to the typical PIE vector table that is present. This allows PIE vector addresses for the new firmware to be populated prior to the LFU switchover. During LFU switchover, a simple swap operation which activates the PIE vector swap table and deactivates the previously active PIE vector table is initiated by user application code, and this operation takes just 1 CPU clock cycle. To initiate the swap, user application code sets LFUConfig.PieVectorSwap = 1. The PIE vector table swap features are also implemented on a redundant PIE vector table implemented for safety. Therefore, to implement PIE vector table swap, the sizes of PIE vector memory and redundant PIE vector memory are both doubled.
The changes are summarized in Figure 3-19. In this device, there exists a duplicate PIE RAM mapped to a different memory address. There are now two physical PIE vector RAM memories – PIE-1 and PIE-2. By default, PIE-1 is active, and mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-2 is inactive, and mapped to addresses 0x0100_0900-0x0100_0AFF.
When user application code initiates a PIE vector table swap by setting LFUConfig.PieVectorSwap = 1, PIE-2 becomes active, and is mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-1 becomes inactive, and is mapped to addresses 0x0100_0900-0x0100_0AFF.
Note that the PIE vector RAM active addresses are always 0x0000_0D00-0x0000_0EFF. The inactive addresses are always 0x0100_0900-0x0100_0AFF. As mentioned above, prior to the LFU switchover, user application code needs to write to the inactive addresses with the PIE vector locations corresponding to the new firmware.
The register bit LFUStatus.PieVectorSwap provides the status of Pie Vector Swap.
The PIE vector RAM utilizes a parity scheme to detect address and data errors.