SLVA959B November   2018  – October 2021 DRV10866 , DRV10963 , DRV10964 , DRV10970 , DRV10974 , DRV10975 , DRV10983 , DRV10983-Q1 , DRV10987 , DRV11873 , DRV3205-Q1 , DRV3220-Q1 , DRV3245E-Q1 , DRV3245Q-Q1 , DRV8301 , DRV8302 , DRV8303 , DRV8304 , DRV8305 , DRV8305-Q1 , DRV8306 , DRV8307 , DRV8308 , DRV8312 , DRV8313 , DRV8320 , DRV8320R , DRV8323 , DRV8323R , DRV8332 , DRV8343-Q1 , DRV8350 , DRV8350R , DRV8353 , DRV8353R , DRV8412 , DRV8701 , DRV8702-Q1 , DRV8702D-Q1 , DRV8703-Q1 , DRV8703D-Q1 , DRV8704 , DRV8711 , DRV8800 , DRV8801 , DRV8801-Q1 , DRV8801A-Q1 , DRV8802 , DRV8802-Q1 , DRV8803 , DRV8804 , DRV8805 , DRV8806 , DRV8811 , DRV8812 , DRV8813 , DRV8814 , DRV8816 , DRV8818 , DRV8821 , DRV8823 , DRV8823-Q1 , DRV8824 , DRV8824-Q1 , DRV8825 , DRV8828 , DRV8829 , DRV8830 , DRV8832 , DRV8832-Q1 , DRV8833 , DRV8833C , DRV8834 , DRV8835 , DRV8836 , DRV8837 , DRV8837C , DRV8838 , DRV8839 , DRV8840 , DRV8841 , DRV8842 , DRV8843 , DRV8844 , DRV8846 , DRV8847 , DRV8848 , DRV8850 , DRV8860 , DRV8870 , DRV8871 , DRV8871-Q1 , DRV8872 , DRV8872-Q1 , DRV8873-Q1 , DRV8880 , DRV8881 , DRV8884 , DRV8885 , DRV8886 , DRV8886AT , DRV8889-Q1

 

  1.   Trademarks
  2. 1Grounding Optimization
    1. 1.1 Frequently Used Terms/Connections
    2. 1.2 Using a Ground Plane
      1. 1.2.1 Two-Layer Board Techniques
    3. 1.3 Common Problems
      1. 1.3.1 Capacitive and Inductive Coupling
      2. 1.3.2 Common and Differential Noise
    4. 1.4 EMC Considerations
  3. 2Thermal Overview
    1. 2.1 PCB Conduction and Convection
    2. 2.2 Continuous Top-Layer Thermal Pad
    3. 2.3 Copper Thickness
    4. 2.4 Thermal Via Connections
    5. 2.5 Thermal Via Width
    6. 2.6 Summary of Thermal Design
  4. 3Vias
    1. 3.1 Via Current Capacity
    2. 3.2 Via Layout Recommendations
      1. 3.2.1 Multi-Via Layout
      2. 3.2.2 Via Placement
  5. 4General Routing Techniques
  6. 5Bulk and Bypass Capacitor Placement
    1. 5.1 Bulk Capacitor Placement
    2. 5.2 Charge Pump Capacitor
    3. 5.3 Bypass/Decoupling Capacitor Placement
      1. 5.3.1 Near Power Supply
      2. 5.3.2 Near Power Stage
      3. 5.3.3 Near Switch Current Source
      4. 5.3.4 Near Current Sense Amplifiers
      5. 5.3.5 Near Voltage Regulators
  7. 6MOSFET Placement and Power Stage Routing
    1. 6.1 Common Power MOSFET Packages
      1. 6.1.1 DPAK
      2. 6.1.2 D2PAK
      3. 6.1.3 TO-220
      4. 6.1.4 8-Pin SON
    2. 6.2 MOSFET Layout Configurations
    3. 6.3 Power Stage Layout Design
      1. 6.3.1 Switch Node
      2. 6.3.2 High-Current Loop Paths
      3. 6.3.3 VDRAIN Sense Pin
  8. 7Current Sense Amplifier Routing
    1. 7.1 Single High-Side Current Shunt
    2. 7.2 Single Low-Side Current Shunt
    3. 7.3 Two-Phase and Three-Phase Current Shunt Amplifiers
    4. 7.4 Component Selection
    5. 7.5 Placement
    6. 7.6 Routing
    7. 7.7 Useful Tools (Net Ties and Differential Pairs)
    8. 7.8 Input and Output Filters
    9. 7.9 Do's and Don'ts
  9. 8References
  10. 9Revision History

4 General Routing Techniques

Follow these general routing techniques when doing a motor driver PCB design:

  • Make gate drive traces wide and as short in length as possible. Start with a trace width of 20 mils for at least a 1 oz copper, more if required by high currents.
    GUID-D42CAEAC-F471-4E82-A461-CEABAD1AAF91-low.gifFigure 4-1 DRV8323xEVM Gate Signal
  • Route the signal trace of the high-side gate and the switch node trace as close as possible to minimize inductance, loop area, and the possibility of noise caused by dv/dt switching.
    GUID-1725196F-F1B1-4E48-B03E-ED5169F6BDB7-low.gifFigure 4-2 Parallel Gate Traces
  • Do not use right-angle traces. A 90 degree bend in a trace an acts as an impedance and can cause the current to reflect. When the phases of the motor are switching, the sharp bends can introduce electromagnetic interference (EMI) issues. Circular bends are ideal but may not be practical in actual designs. The best practice for corner routing is to use obtuse angles. Figure 4-3 shows different examples of angles in traces.
    GUID-3EEEC200-88AA-40E5-9322-4CA6FF3F493A-low.gifFigure 4-3 Right Angle Trace
  • Transition vias to pads, specifically from thin to thick traces on the output pins. The teardrop technique decreases the thermal stress of the signal transition. This technique also avoids crack of the traces and makes the trace more robust mechanically. The teardrop technique is applicable when going from a small signal to a through-hole pad.
    GUID-0882EAB2-E1AD-4432-B8C3-C217E98FEF83-low.gifFigure 4-4 Transitioning Vias to Pads
  • Route traces in parallel pairs when routing around an object to avoid differential impedance and discontinuities caused by split traces. This method is important for the signals of the current sense amplifiers.
    GUID-44291D8D-7B77-4254-B66B-C5FA253F3A01-low.gifFigure 4-5 Routing Parallel Traces
  • Place passive components within the signal path, such as source-matching resistors or ac-coupling capacitors, and next to each other. Placing components in parallel creates wider traces spacing. Staggering components is not recommended as it creates narrow areas.
    GUID-69C0F07F-63EE-49A6-97B4-3BB05FA61426-low.gifFigure 4-6 Recommended Component Placing
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression.
    GUID-6B5A48F3-9ECF-43F0-BB3C-10B87B17787D-low.gifFigure 4-7 Analog and Digital Ground Separation