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DP83843

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10/100-Mbps Ethernet PHY transceiver with fiber & AUI support

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Data sheet

DP83843

ACTIVE
Data sheet Order now

Product details

Datarate (Mbps) 10/100 Interface type MII, SNI Number of ports Single Rating Catalog Features AUI support, FX support Supply voltage (V) 5 I/O supply voltage (typ) (V) 5 Operating temperature range (°C) 0 to 70
Datarate (Mbps) 10/100 Interface type MII, SNI Number of ports Single Rating Catalog Features AUI support, FX support Supply voltage (V) 5 I/O supply voltage (typ) (V) 5 Operating temperature range (°C) 0 to 70
QFP (NNC) 80 295.84 mm² 17.2 x 17.2
  • IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
    and built-in filters
  • IEEE 802.3u 100BASE-TX compatible - directly drives
    standard Category 5 UTP, no need for external
    100BASE-TX transceiver
  • Fully Integrated and fully compliant ANSI X3.263 TPPMD
    physical sublayer which includes adaptive equalization
    and BLW compensation
  • IEEE 802.3u 100BASE-FX compatible - connects directly
    to industry standard Electrical/Optical transceivers
  • IEEE 802.3u Auto-Negotiation for automatic speed selection
  • IEEE 802.3u compatible Media Independent Interface
    (MII) with Serial Management Interface
  • Integrated high performance 100 Mb/s clock recovery
    circuitry requiring no external filters
  • Full Duplex support for 10 and 100 Mb/s data rates
  • MII Serial 10 Mb/s mode
  • Fully configurable node/switch and 100Mb/s repeater
    modes
  • Programmable loopback modes for flexible systemdiagnostics
  • Flexible LED support
  • Single register access to complete PHY status
  • MDIO interrupt support
  • Individualized scrambler seed for 100BASE-TX applications
    using multiple PHYs
  • Low power consumption for multi-port applications
  • Small footprint 80-pin PQFP package
  • IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
    and built-in filters
  • IEEE 802.3u 100BASE-TX compatible - directly drives
    standard Category 5 UTP, no need for external
    100BASE-TX transceiver
  • Fully Integrated and fully compliant ANSI X3.263 TPPMD
    physical sublayer which includes adaptive equalization
    and BLW compensation
  • IEEE 802.3u 100BASE-FX compatible - connects directly
    to industry standard Electrical/Optical transceivers
  • IEEE 802.3u Auto-Negotiation for automatic speed selection
  • IEEE 802.3u compatible Media Independent Interface
    (MII) with Serial Management Interface
  • Integrated high performance 100 Mb/s clock recovery
    circuitry requiring no external filters
  • Full Duplex support for 10 and 100 Mb/s data rates
  • MII Serial 10 Mb/s mode
  • Fully configurable node/switch and 100Mb/s repeater
    modes
  • Programmable loopback modes for flexible systemdiagnostics
  • Flexible LED support
  • Single register access to complete PHY status
  • MDIO interrupt support
  • Individualized scrambler seed for 100BASE-TX applications
    using multiple PHYs
  • Low power consumption for multi-port applications
  • Small footprint 80-pin PQFP package

The DP83843BVJE is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols.

This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber media via industry standard electrical/optical fiber PMD transceivers. This device also interfaces directly to the MAC layer through the IEEE 802.3u standard Media Independent Interface (MII), ensuring interoperability between products from different vendors.

The DP83843 is designed with National Semiconductor’s advanced CMOS process. Its system architecture is based on the integration of several of National's industry proven core technologies:

  • IEEE 802.3 ENDEC with AUI/10BASE-T transceiver module to provide the 10 Mb/s functions
  • Clock Recovery/Generator Modules fromNational's Fast Ethernet and FDDI products
  • FDDI Stream Cipher scrambler/descrambler for TP-PMD
  • 100BASE-Xphysical codingsub-layer (PCS) andcontrol logic that integrates the core modules into a dual speed Ethernet physical layer controller
  • ANSI X3T12 Compliant TP-PMD Transceiver technology with Baseline Wander (BLW) compensation

The DP83843BVJE is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols.

This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber media via industry standard electrical/optical fiber PMD transceivers. This device also interfaces directly to the MAC layer through the IEEE 802.3u standard Media Independent Interface (MII), ensuring interoperability between products from different vendors.

The DP83843 is designed with National Semiconductor’s advanced CMOS process. Its system architecture is based on the integration of several of National's industry proven core technologies:

  • IEEE 802.3 ENDEC with AUI/10BASE-T transceiver module to provide the 10 Mb/s functions
  • Clock Recovery/Generator Modules fromNational's Fast Ethernet and FDDI products
  • FDDI Stream Cipher scrambler/descrambler for TP-PMD
  • 100BASE-Xphysical codingsub-layer (PCS) andcontrol logic that integrates the core modules into a dual speed Ethernet physical layer controller
  • ANSI X3T12 Compliant TP-PMD Transceiver technology with Baseline Wander (BLW) compensation
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Technical documentation

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Type Title Date
* Data sheet DP83843 PHYTER datasheet (Rev. B) 13 Nov 2013
More literature How to Pass IEEE Ethernet Compliance Tests PDF | HTML 20 Sep 2021
More literature AN-1506 DP83843 to DP83848C/I/YB PHYTER System Rollover Document (Rev. A) 26 Apr 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Driver or library

ETHERNET-SW — Ethernet PHY Linux drivers & tools

The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.

The USB-2-MDIO software lets you directly access the registers during debug and (...)

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Simulation model

DP83843 IBIS Model

SNLM101.ZIP (24 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
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QFP (NNC) 80 View options

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