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DP83561-SP

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Space grade (QMLV-RHA) 10/100/1000 Ethernet PHY with SEFI monitoring suite

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Data sheet

DP83561-SP

ACTIVE
Data sheet Order now

Product details

Datarate (Mbps) 10/100/1000 Interface type MII, RGMII Rating Space Number of ports Single Features QMLV-RHA compliant, Space Qualified I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -55 to 125 Number of LEDs 3 ESD HBM (kV) 8
Datarate (Mbps) 10/100/1000 Interface type MII, RGMII Rating Space Number of ports Single Features QMLV-RHA compliant, Space Qualified I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -55 to 125 Number of LEDs 3 ESD HBM (kV) 8
CFP (HBE) 64 118.81 mm² 10.9 x 10.9
  • QML Class V (QMLV), RHA, SMD 5962-20216
  • Military temperature range: –55°C to 125°C
  • Radiation performance
    • RHA up to TID = 300 krad (Si)
    • SEL immune to LET = 121 MeV·cm2/mg
  • Single Event Functional Interrupt (SEFI) monitor suite
    • Monitor
      • IEEE PCS state machine monitors
      • ECC configuration register monitor
      • PLL lock monitor
      • On-chip temperature monitor
    • Action
      • Interrupt pins to monitor events
    • Correction
      • ECC-protected configuration registers
      • Pin-configurable automatic SEFI recovery
      • Serial Management Interface (SMI) disable
  • Fully compatible to IEEE802.3 1000BASE-T, 100BASE-TX and 10BASE-Te specifications
  • Low RGMII latency (Tx < 90 ns, Rx < 290 ns)
  • Time sensitive network compliant
  • MAC interface: RGMII, MII
  • Integrated MDI termination resistors
  • Programmable RGMII termination impedance
  • Power supply: 2.5 V, 1.8 V, 1.1 V
  • I/O voltages: 1.8 V, 2.5 V, and 3.3 V
  • 25-MHz or 125-MHz synchronized clock output
  • Cable diagnostics: open, short using TDR
  • JTAG support
  • QML Class V (QMLV), RHA, SMD 5962-20216
  • Military temperature range: –55°C to 125°C
  • Radiation performance
    • RHA up to TID = 300 krad (Si)
    • SEL immune to LET = 121 MeV·cm2/mg
  • Single Event Functional Interrupt (SEFI) monitor suite
    • Monitor
      • IEEE PCS state machine monitors
      • ECC configuration register monitor
      • PLL lock monitor
      • On-chip temperature monitor
    • Action
      • Interrupt pins to monitor events
    • Correction
      • ECC-protected configuration registers
      • Pin-configurable automatic SEFI recovery
      • Serial Management Interface (SMI) disable
  • Fully compatible to IEEE802.3 1000BASE-T, 100BASE-TX and 10BASE-Te specifications
  • Low RGMII latency (Tx < 90 ns, Rx < 290 ns)
  • Time sensitive network compliant
  • MAC interface: RGMII, MII
  • Integrated MDI termination resistors
  • Programmable RGMII termination impedance
  • Power supply: 2.5 V, 1.8 V, 1.1 V
  • I/O voltages: 1.8 V, 2.5 V, and 3.3 V
  • 25-MHz or 125-MHz synchronized clock output
  • Cable diagnostics: open, short using TDR
  • JTAG support

The DP83561-SP is a high reliability gigabit ethernet PHY designed for the high-radiation environment of space. The DP83561-SP is a low power, fully featured physical layer transceiver with integrated PMD sub-layers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83561-SP is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs in extremely hostile environments. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) and MII.

The device is Radiation Hardened by Design (RHBD), fabricated by Texas Instruments using a CMOS process, and is available in 64-pin Ceramic Quad Flat Pack (CQFP) package, with a 11-mm × 11-mm body size (nominal).

The DP83561-SP is a high reliability gigabit ethernet PHY designed for the high-radiation environment of space. The DP83561-SP is a low power, fully featured physical layer transceiver with integrated PMD sub-layers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83561-SP is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs in extremely hostile environments. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) and MII.

The device is Radiation Hardened by Design (RHBD), fabricated by Texas Instruments using a CMOS process, and is available in 64-pin Ceramic Quad Flat Pack (CQFP) package, with a 11-mm × 11-mm body size (nominal).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet DP83561-SP Radiation-Hardness-Assured (RHA), 10/100/1000 Ethernet PHY Transceiver with SEFI Handling Sub-System datasheet (Rev. B) PDF | HTML 12 Nov 2021
* Radiation & reliability report DP83561-SP Single Event Effects (SEE) Radiation Report (Rev. A) PDF | HTML 01 Apr 2025
* Radiation & reliability report DP83561-SP Radiation-Hardness-Assured (RHA), 10/100/1000 Ethernet 14 Jun 2022
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17 Jun 2025
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10 Jun 2025
Selection guide TI Space Products (Rev. K) 04 Apr 2025
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20 Feb 2025
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Application note How to Pass IEEE Ethernet Compliance Tests PDF | HTML 20 Sep 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DP83561EVM — Space qualified (QMLV-RHA compliant) 10/100/1000 Ethernet PHY evaluation module

The DP83561-EVM is an evaluation board designed to demonstrate the performance and unique features of the DP83561-SP Space-grade ethernet physical layer transceiver.
User guide: PDF | HTML
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Driver or library

ETHERNET-SW — Ethernet PHY drivers & tools

The drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers. Linux and RTOS drivers can be found on our github.

 

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Support software

USB-2-MDIO — USB-2-MDIO Tool v1.0

The USB-2-MDIO software tool lets Texas Instruments' Ethernet PHYs access the MDIO status and device control registers.  The USB-2-MDIO tool includes a LaunchPad™ Development kit for TI's MSP430™ MCUs that is interfaced with a lightweight GUI.  The (...)

Supported products & hardware

Supported products & hardware
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Simulation model

DP83561-SP IBIS Model

SNLM248.ZIP (727 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
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CFP (HBE) 64 Ultra Librarian
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