LMK04010

ACTIVE

Low-Noise Clock Jitter Cleaner with Cascaded PLLs

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Product details

Parameters

Function Cascaded PLLs Number of outputs 5 Number of Inputs 2 RMS jitter 0.1 Output frequency (Min) (MHz) 0.29 Output frequency (Max) (MHz) 1296 Input type LVCMOS, LVDS, LVPECL Output type LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features Integrated VCO Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • Cascaded PLLatinum PLL Architecture
  • PLL1
  • Phase detector rate of up to 40 MHz
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Dual redundant input reference clock with LOS
  • PLL2
  • Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
  • Phase detector rate up to 100 MHz
  • Input frequency-doubler
  • Integrated Low-Noise VCO
  • Ultra-Low RMS Jitter Performance
  • 150 fs RMS jitter (12 kHz – 20 MHz)
  • 200 fs RMS jitter (100 Hz – 20 MHz)
  • LVPECL/2VPECL, LVDS, and LVCMOS outputs
  • Support clock rates up to 1080 MHz
  • Default Clock Output (CLKout2) at power up
  • Five dedicated channel divider and delay blocks
  • Pin compatible family of clocking devices
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Wireless Infrastructure
  • Networking, SONET/SDH, DSLAM
  • Medical
  • Military / Aerospace
  • Test and Measurement
  • Video

  • open-in-new Find other Clock jitter cleaners & synchronizers

    Description

    The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

    The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

    The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.


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    Technical documentation

    = Top documentation for this product selected by TI
    No results found. Please clear your search and try again. View all 5
    Type Title Date
    * Datasheet LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs datasheet (Rev. J) Sep. 19, 2011
    Technical articles Solving synchronization challenges in Industrial Ethernet Jul. 19, 2019
    Application notes AN-1910 LMK04000 Family Phase Noise Characterization (Rev. A) Apr. 26, 2013
    Application notes AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) Apr. 26, 2013
    User guides Clock Conditioner Owner's Manual Nov. 10, 2006

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Software development

    APPLICATION SOFTWARE & FRAMEWORKS Download
    Clock Design Tool - Loop Filter & Device Configuration + Simulation
    CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
    IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
    CodeLoader Software for device register programming
    CODELOADER The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


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    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
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    CAD/CAE symbols

    Package Pins Download
    WQFN (RHS) 48 View options

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