Product details

Function Clock divider Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 3100 Number of outputs 12 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 3 Features Pin programmable, uWire Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS, LVDS, LVPECL Input type LVDS
Function Clock divider Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 3100 Number of outputs 12 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 3 Features Pin programmable, uWire Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS, LVDS, LVPECL Input type LVDS
WQFN (RHS) 48 49 mm² 7 x 7
  • Pin control mode or MICROWIRE (SPI)
  • Input and output frequency range: 1 kHz to 3.1 GHz
  • Separate input for clock output banks A and B
  • 14 differential clock outputs in two banks (A and B)
    • Output Bank A
      • 8 differential, programmable outputs (up to 8 as LVCMOS)
      • Divider values of 1 to 8, even and odd.
    • Output Bank B
      • 6 differential outputs (or up to 12 as LVCMOS)
      • Divides values of 1 to 1045 or 1 to 8, even and odd
      • Analog and digital delays
  • 50% duty cycle on all outputs for all divides
  • Separate synchronization of bank A and B.
  • RMS additive jitter 50 fs at 800 MHz
    • 50-fs RMS additive jitter (12 kHz to 20 MHz)
  • Industrial temperature range: –40°C to 85°C
  • 3.15-V to 3.45-V Operation
  • Pin control mode or MICROWIRE (SPI)
  • Input and output frequency range: 1 kHz to 3.1 GHz
  • Separate input for clock output banks A and B
  • 14 differential clock outputs in two banks (A and B)
    • Output Bank A
      • 8 differential, programmable outputs (up to 8 as LVCMOS)
      • Divider values of 1 to 8, even and odd.
    • Output Bank B
      • 6 differential outputs (or up to 12 as LVCMOS)
      • Divides values of 1 to 1045 or 1 to 8, even and odd
      • Analog and digital delays
  • 50% duty cycle on all outputs for all divides
  • Separate synchronization of bank A and B.
  • RMS additive jitter 50 fs at 800 MHz
    • 50-fs RMS additive jitter (12 kHz to 20 MHz)
  • Industrial temperature range: –40°C to 85°C
  • 3.15-V to 3.45-V Operation

The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency division of precision clocks.

The LMK01801 features extremely low residual noise, frequency division, digital and analog delay adjustments, and fourteen (14) programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential output).

The LMK01801 features two independent inputs that can be driven differentially (LVDS, LVPECL) or in single-ended mode (LVCMOS, RF Sinewave). The first input drives output Bank A consisting of eight (8) outputs. The second input drives output Bank B consisting of six (6) outputs.

The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency division of precision clocks.

The LMK01801 features extremely low residual noise, frequency division, digital and analog delay adjustments, and fourteen (14) programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential output).

The LMK01801 features two independent inputs that can be driven differentially (LVDS, LVPECL) or in single-ended mode (LVCMOS, RF Sinewave). The first input drives output Bank A consisting of eight (8) outputs. The second input drives output Bank B consisting of six (6) outputs.

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Technical documentation

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Type Title Date
* Data sheet LMK01801 Dual Clock Divider Buffer datasheet (Rev. D) 30 Sep 2021
EVM User's guide LMK01801BEVAL Evaluation Board Operating Instructions (Rev. A) 28 Feb 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK01801BEVAL — LMK01801 Dual Clock Divider Buffer Evaluation Module

The LMK01801 Evaluation Kit simplifies evaluation of the LMK01801 3.1 GHz Dual Clock Divider Buffer. The package consists of an Evaluation Board, Evaluation Board Instructions, and a cable for programming the device through a PC parallel port. CodeLoader 4 is the software used to program the (...)
Not available on TI.com
Application software & framework

CLOCKDESIGNTOOL — Clock Design Tool - Loop Filter & Device Configuration + Simulation

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
IDE, configuration, compiler or debugger

CODELOADER — CodeLoader Software for device register programming

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


Which software do I use?

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Simulation model

LMK01801 IBIS Model (Rev. A)

SNAM094A.ZIP (63 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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WQFN (RHS) 48 View options

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