Product details

Function Dual-loop PLL Number of outputs 7 RMS jitter (fs) 100 Output frequency (Min) (MHz) 0.22 Output frequency (Max) (MHz) 2600 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features 0 Delay Operating temperature range (C) -40 to 85
Function Dual-loop PLL Number of outputs 7 RMS jitter (fs) 100 Output frequency (Min) (MHz) 0.22 Output frequency (Max) (MHz) 2600 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features 0 Delay Operating temperature range (C) -40 to 85
WQFN (NKD) 64 81 mm² 9 x 9
  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator Circuit
      • Holdover Mode when Input Clocks are Lost
        • Automatic or Manual Triggering/Recovery
    • PLL2
      • Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
      • Phase Detector Rate up to 155 MHz
      • OSCin Frequency-doubler
      • Integrated Low-Noise VCO
  • 3 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Precision Digital Delay, Fixed or Dynamically Adjustable
  • 25-ps Step Analog Delay Control.
  • 6 Differential Outputs. Up to 12 Single Ended.
    • Up to 5 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85 °C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9 mm × 9 mm × 0.8 mm)
  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator Circuit
      • Holdover Mode when Input Clocks are Lost
        • Automatic or Manual Triggering/Recovery
    • PLL2
      • Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
      • Phase Detector Rate up to 155 MHz
      • OSCin Frequency-doubler
      • Integrated Low-Noise VCO
  • 3 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Precision Digital Delay, Fixed or Dynamically Adjustable
  • 25-ps Step Analog Delay Control.
  • 6 Differential Outputs. Up to 12 Single Ended.
    • Up to 5 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85 °C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9 mm × 9 mm × 0.8 mm)

The LMK04906 is the industry’s highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock inputs ranging from 1 kHz to 500 MHz and generates 6 unique clock output frequencies ranging from 284 kHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.

The device provides virtually all frequency translation combinations required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.

The LMK04906 is the industry’s highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock inputs ranging from 1 kHz to 500 MHz and generates 6 unique clock output frequencies ranging from 284 kHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.

The device provides virtually all frequency translation combinations required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.

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Technical documentation

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Type Title Date
* Data sheet LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With 6 Programmable Outputs datasheet (Rev. F) 11 Aug 2017
EVM User's guide LMK04906 Evaluation Board User's Guide (Rev. A) 26 Nov 2013
Application note Using the LMK0480x/LMK04906 for Hitless Switching and Holdover 12 Jul 2013
Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) 26 Apr 2013
Design guide Clock Conditioner Owner's Manual 10 Nov 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK04906BEVAL — Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO

The LMK04906 is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low (...)

Not available on TI.com
Application software & framework

CLOCKDESIGNTOOL — Clock Design Tool - Loop Filter & Device Configuration + Simulation

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
IDE, configuration, compiler or debugger

CODELOADER — CodeLoader Software for device register programming

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


Which software do I use?

Product

(...)

Simulation model

LMK04906 IBIS Model (Rev. C)

SNAM101C.ZIP (106 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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WQFN (NKD) 64 View options

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