Product details


Function Fanout Additive RMS jitter (Typ) (fs) 51 Output frequency (Max) (MHz) 3100 Number of outputs 7 VCC out (V) 2.5, 3.3 VCC core (V) 3.3 Output skew (ps) 50 Features Pin programmable Operating temperature range (C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL open-in-new Find other Clock buffers


  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz
      and Accept LVPECL, LVDS, CML, SSTL,
      HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10 to 40 MHz
      Crystal or Single-Ended Clock
  • Two Banks with 3 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable
      Per Bank)
    • LVPECL Additive Jitter with LMK03806 Clock
      Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at
    156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V
    ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 36-lead WQFN (6 mm × 6 mm)
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The LMK00306 is a 3-GHz, 6-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 3 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00306 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00306 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

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Technical documentation

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Type Title Date
* Datasheet LMK00306 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator datasheet (Rev. D) Mar. 28, 2016
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
User guides LMK00306 Evaluation Module User Guide Mar. 06, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The LMK00306 Evaluation Board allows functional and performance verification of the LMK00306 high-performance 6-output differential clock buffer device.

  • Low-noise clock fan-out with two banks of three differential outputs each and one LVCMOS output
  • Selectable differential output type (LVPECL, LVDS, HCSL, or Hi-Z), selectable per bank via control pins
  • 3:1 input multiplexer with two universal input buffers and one crystal oscillator interface (...)

Software development

Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

Design tools & simulation

SNAM049A.ZIP (105 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
(NJK) 36 View options

Ordering & quality

Support & training

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If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​


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