LMK02002

ACTIVE

1 to 800-MHz, precision clock distributor with integrated PLL and 4 LVPECL outputs

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Product details

Parameters

Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Clock generators

Features

  • 20 fs additive jitter
  • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
  • Clock output frequency range of 1 to 800 MHz
  • 4 LVPECL clock outputs
  • Dedicated divider and delay blocks on each clock output
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Networking, SONET/SDH, DSLAM
  • Wireless Infrastructure
  • Medical
  • Test and Measurement
  • Military / Aerospace

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    Description

    The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks.

    Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

    The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.


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    Technical documentation

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    Type Title Date
    * Data sheet LMK02002 Precision Clock Conditioner with Integrated PLL datasheet Aug. 16, 2007
    Technical article How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
    Technical article Clocking sampled systems to minimize jitter Jul. 31, 2014
    Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
    Application note AN-1821 CPRI Repeater System (Rev. A) Apr. 26, 2013
    User guide Clock Conditioner Owner's Manual Nov. 10, 2006

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Software development

    APPLICATION SOFTWARE & FRAMEWORK Download
    Clock Design Tool - Loop Filter & Device Configuration + Simulation
    CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
    APPLICATION SOFTWARE & FRAMEWORK Download
    Texas Instruments Clocks and Synthesizers (TICS) Pro Software
    TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
    Features
    • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
    • Export programming configurations for use in end application.
    IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
    CodeLoader Software for device register programming
    CODELOADER The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


    Which software do I use?

    Product

    Loop (...)

    Design tools & simulation

    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    DESIGN TOOL Download
    Clock tree architect programming software
    CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
    Features
    • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
    • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
    • Presents clear and intuitive block (...)

    CAD/CAE symbols

    Package Pins Download
    WQFN (RHS) 48 View options

    Ordering & quality

    Information included:
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    • Device marking
    • Lead finish/Ball material
    • MSL rating/Peak reflow
    • MTBF/FIT estimates
    • Material content
    • Qualification summary
    • Ongoing reliability monitoring

    Support & training

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