Product details

Number of outputs 4 Output type LVPECL Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
Number of outputs 4 Output type LVPECL Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7

  • 20 fs additive jitter
  • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
  • Clock output frequency range of 1 to 800 MHz
  • 4 LVPECL clock outputs
  • Dedicated divider and delay blocks on each clock output
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Networking, SONET/SDH, DSLAM
  • Wireless Infrastructure
  • Medical
  • Test and Measurement
  • Military / Aerospace

  • 20 fs additive jitter
  • Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
  • Clock output frequency range of 1 to 800 MHz
  • 4 LVPECL clock outputs
  • Dedicated divider and delay blocks on each clock output
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

  • Target Applications

  • Data Converter Clocking
  • Networking, SONET/SDH, DSLAM
  • Wireless Infrastructure
  • Medical
  • Test and Measurement
  • Military / Aerospace

  • The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks.

    Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

    The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.


    The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks.

    Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

    The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.


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    Technical documentation

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    Top documentation Type Title Format options Date
    * Data sheet LMK02002 Precision Clock Conditioner with Integrated PLL datasheet 16 Aug 2007
    Application note AN-1821 CPRI Repeater System (Rev. A) 26 Apr 2013
    Design guide Clock Conditioner Owner's Manual 10 Nov 2006

    Design & development

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    Software programming tool

    CODELOADER CodeLoader Device Register Programming v4.19.0

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    Support software

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    Design tool

    CLOCK-TREE-ARCHITECT — Clock tree architect programming software

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    Simulation tool

    PSPICE-FOR-TI — PSpice® for TI design and simulation tool

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    Package Pins CAD symbols, footprints & 3D models
    WQFN (RHS) 48 Ultra Librarian

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