Product details


Number of supplies monitored 4 Threshold voltage 1 (Typ) (V) Adjustable Features Manual reset capable, Negative voltage monitoring, Undervoltage and overvoltage monitor, Watchdog timer Reset threshold accuracy (%) 1 Output driver type/reset output Active-low, Open-drain Time delay (ms) 20, 300, Programmable Rating Catalog Watchdog timer WDI (sec) 0.6 Operating temperature range (C) -40 to 125 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

VQFN (RGP) 20 16 mm² 4 x 4 open-in-new Find other Supervisor & reset ICs


  • Four Independent Voltage Supervisors
  • Channel 1:
    • Adjustable Threshold Down to 0.4 V
    • Manual Reset (MR) Input
  • Channels 2, 3:
    • Adjustable Threshold Down to 0.4 V
  • Channel 4:
    • Adjustable Threshold at Any Positive or Negative Voltage
    • Window Comparator
  • Adjustable Delay Time: 1.4 ms to 10 s
  • Threshold Accuracy: 0.25% Typical
  • Very Low Quiescent Current: 11 µA Typical
  • Watchdog Timer With Dedicated Output
  • Well-Controlled Output During Power Up
  • TPS386000: Open-Drain RESETn and WDO
  • TPS386040: Push-Pull RESETn and WDO
  • Package: 4-mm × 4-mm, 20-Pin VQFN
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The TPS3860x0 family of supply voltage supervisors (SVSs) can monitor four power rails that are greater than 0.4 V and one power rail less than 0.4 V (including negative voltage) with a 0.25% (typical) threshold accuracy. Each of the four supervisory circuits (SVS-n) assert a RESETn or RESETn output signal when the SENSEm input voltage drops below the programmed threshold. With external resistors, the threshold of each SVS-n can be programmed (where n = 1, 2, 3, 4 and m = 1, 2, 3, 4L, 4H).

Each SVS-n has a programmable delay before releasing RESETn or RESETn. The delay time can be set independently for each SVS from 1.4 ms to 10 s through the CTn pin connection. Only SVS-1 has an active-low manual reset (MR) input; a logic-low input to MR asserts RESET1 or RESET1.

SVS-4 monitors the threshold window using two comparators. The extra comparator can be configured as a fifth SVS to monitor negative voltage with voltage reference output VREF.

The TPS3860x0 has a very low quiescent current of 11 µA (typical) and is available in a small, 4-mm x 4-mm, VQFN-20 package.

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Technical documentation

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Type Title Date
* Data sheet TPS386000 and TPS386040 Quad Supply Voltage Supervisors With Adjustable Delay and Watchdog Timer datasheet (Rev. F) Oct. 03, 2018
Application note Voltage and Processor Monitoring Solutions in Factory Automation and Control App (Rev. A) Aug. 05, 2021
Application note Optimizing Resistor Dividers at a Comparator (Rev. B) Apr. 30, 2021
Technical article Monitoring 12-V automotive battery systems: Load-dump, cold-crank and false-reset management Mar. 24, 2021
Selection guide Voltage Supervisors (Reset ICs) Quick Reference Guide (Rev. H) Feb. 28, 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
Application note Creating a Sequencing Voltage Supervisor (Reset IC) Using TPS386000 and LM3880 May 14, 2019
Application note Comparing Voltage and Processor Monitoring Solutions Apr. 05, 2019
Technical article Tips and tricks for optimizing your voltage supervisor Mar. 07, 2017
Application note Analog Applications Journal 4Q 2014 Oct. 24, 2014
Application note Power-supply sequencing for FPGAs Oct. 24, 2014
Technical article Develop a more efficient energy grid power supply Jun. 07, 2014
Application note Setting the SVS Voltage Monitor Threshold May 23, 2012
Application note Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs Sep. 19, 2011
User guide TPS3860xxEVM-736 User's Guide Mar. 29, 2011
User guide User's Guide for the TPS386000 and TPS386040 EVM Sep. 10, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
The TPS386000EVM-736 evaluation module (EVM) is a fully assembled and tested circuit for evaluating the TPS386000 quad supply voltage supervisor in a 20-pin QFN package. The TPS386000EVM-736 can be customized by changing resistor values to monitor any voltage greater than 0.4 V, including (...)
  • 4 complete SVS modules on 1 silicon platform
  • Programmable delay time: 1.4 ms to 10 s
  • Very-low quiescent current: 12 µA (typical)
  • Threshold accuracy: 0.25% (typical)
  • SVS-1: manual reset (MR) input
  • SVS-1,2,3: adjustable threshold down to 0.4 V
  • SVS-4: adjustable threshold at any positive or negative voltage (...)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025 This reference design implements hardware interface based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows you to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designs with a low (...)
document-generic Schematic
High fidelity, near-field two-way audio reference design with noise reduction and echo cancellation
TIDA-01589 — Man machine interaction requires an acoustic interface for providing full duplex hands-free communication. In hands-free mode, part of the far-end or near-end audio signal from the speaker is coupled to the microphones. Furthermore, in noisy environments the microphones also capture ambient noise in (...)
document-generic Schematic
ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022 Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
document-generic Schematic
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable.  It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
document-generic Schematic
EnDat 2.2 System Reference Design
TIDEP0050 This reference design implements EnDat 2.2 Master protocol stack and hardware interface based on HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of EnDat 2.2 Master protocol stack, half-duplex communications using RS-485 transceivers and the line termination (...)
document-generic Schematic

CAD/CAE symbols

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