Enhanced Low Input (2.25V-5.5V) up to 1MHz Frequency, Sync. Buck Controller, source/sink

TPS40021 is not recommended for new designs.
This product continues to be in production to support existing customers. Please consider one of these alternatives:
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Similar but not functionally equivalent to the compared device:
TPS40077 ACTIVE 4.5-V to 28-V, synchronous buck controller with voltage feed forward in HTSSOP package 4.5 to 28-Vin controller with programmable (up to 1-MHz) switching frequency in 3-mm x 3-mm QFN package.
TPS40303 ACTIVE 3-V to 20-V, 25-A, 300-kHz synchronous buck controller with FSS 3 to 20-Vin controller with 300-kHz switching frequency in 3-mm x 3-mm QFN package.
TPS40304 ACTIVE 3-V to 20-V, 25-A, 600-kHz synchronous buck controller with FSS 3 to 20-Vin controller with 600-kHz switching frequency in 3-mm x 3-mm QFN package.
TPS40305 ACTIVE 3-V to 20-V, 25-A, 1.2-MHz synchronous buck controller with FSS 3 to 20-Vin controller with 1.2-MHz switching frequency in 3-mm x 3-mm QFN package.

Product details


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  • Operating Input Voltage 2.25 V to 5.5 V
  • Output Voltage as Low as 0.7 V
  • 1% Internal 0.7 V Reference
  • Predictive Gate Drive™ N-Channel MOSFET Drivers for Higher Efficiency
  • Externally Adjustable Soft-Start and Short Circuit Current Limit
  • Programmable Fixed-Frequency 100 kHz-to-1 MHz Voltage-Mode Control
  • Source-Only Current or Source/Sink Current
  • Quick Response Output Transient Comparators with Power Good Indication Provide Output Status
  • 16-Pin PowerPAD™ Package
    • Networking Equipment
    • Telecom Equipment
    • Base Stations
    • Servers
    • DSP Power

PowerPAD and Predictive Gate Drive are trademarks of Texas Instruments.

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The TPS4002x family of dc-to-dc controllers are designed for non-isolated synchronous buck regulators, providing enhanced operation and design flexability through user programmability.

The TPS4002x utilizes a proprietary Predictive Gate Drive™ technology to minimize the diode conduction losses associated with the high-side and synchronous rectifier N-channel MOSFET transistions. The integrated charge pump with boost circuit provides a regulated 5-V gate drive for both the high side and synchronous rectifier N-channel MOSFETs. The use of the Predictive Gate Drive™ technology and charge pump/boost circuits combine to provide a highly efficient, smaller and less expensive converter.

Design flexibility is provided through user programmability of such functions as: operating frequency, short circuit current detection thresholds, soft-start ramp time, and external synchronization frequency. The operating frequency is programmable using a single resistor over a frequency range of 100 kHz to 1 MHz. Higher operating frequencies yield smaller component values for a given converter power level as well as faster loop closure.

The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output every seventh (7th) soft-start cycle.

In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety of output L-C component values.

The output voltage transient comparators provide a quick response, first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters. The transient comparators can be disabled by simply tying the OSNS pin to VDD.

The TPS4002X can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.

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Technical documentation

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Type Title Date
* Data sheet TPS40020 Synchronous Buck Controller datasheet (Rev. D) May 31, 2007
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
More literature Исходные проекты ll May 13, 2011
User guide Using the TPS40021 (TPS40021EVM-001) PR102 (Rev. A) Nov. 18, 2003

Design & development

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Design tools & simulation

SLUM174.TSC (270 KB) - TINA-TI Reference Design
SLUM175.ZIP (61 KB) - TINA-TI Spice Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SLUC263D.ZIP (131 KB)

Reference designs

Reference Design for Telecom Applications (.9V @ .5A)
PMP4742 PMP4742.1 comprises a negative input (-10.8V to -13.2V) to positive output (12V@1A average) inverting buck-boost converter with TPS40210; a hot swap circuit with TPS2420 quickly limits the output current to 2A peak.
Design files
Sync Buck for communications (5V @ 200mA)
PMP5239 — PMP5239 provides 1.8V at 18A off 3.3V using TPS40021 plus NexFETs. Also 5V at 200mA provided by TPS61027.
Design files
TPS40021, 1.25V @ 6Amps
PMP4513 — synchronous buck for core voltage use at I/O input voltage, first benchmark of NexFETs at TI in 2009 shows best in class efficiency
Design files

CAD/CAE symbols

Package Pins Download
HTSSOP (PWP) 16 View options

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