SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The USB3 PHY interface can be connected to either SerDes0 Lane 3 or SerDes4 Lane 3 as required by the application. The CTRL_MMR0 USB0_CTRL.serdes_sel bit determines the SerDes0 lane usage. (This defaults to a value of 1'b0 which selects SerDes0 Ln3.) The appropriate SerDes lane interface (IP3) must also be correctly configured. (e.g. CTRL_MMR0 SERDES0_LN3_CTRL.lane_func_sel = 2'b10 if SerDes0 Ln3 is used or CTRL_MMR0 SERDES4_LN3_CTRL.lane_func_sel = 2'b10 if SerDes4 Ln3 is used.)