SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The reference clocks MCU_PLL0_REF_CLK, MCU_PLL1_REF_CLK and MCU_PLL2_REF_CLK for the PLLs in MCU domain is chosen between the internal high-frequency (HF) oscillator with external crystal, WKUP_HFOSC0, and 12.5-MHz free-running RC oscillator. The selection for all PLLs is made through CTRLMMR_WKUP_MCU_PLL_CLKSEL[8] CLKLOSS_SWTCH_EN, see Table 5-40.
CTRLMMR_WKUP_MCU_PLL_CLKSEL(2)[8] CLKLOSS_SWTCH_EN | MCU_PLLn_REF_CLK(1) |
---|---|
0 (default) | WKUP_HFOSC0_CLK |
1 | WKUP_CLK_12M_RC if clock loss is detected or WKUP_HFOSC0_CLK if clock loss is not detected |