SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The TPIU export path via dedicated pins requires no additional support from SoC functional layers with the exception of any pin multiplexing of application functions and trace at the pins themselves.
Export via the TBRs will intrude on the application domain. For export over all high performance functional interfaces other than USB (such as Ethernet or PCIe), the standard data available event from the TBR / DEBUGCELL can be used by system and/or packet DMA to signal that a buffer of trace data is ready to be transferred. Two dedicated PDMA modules are deployed to allow trace data to be drained from the TBRs in each DEBUGCELL and eventually exported via high speed various functional interfaces. These PDMAs have dedicated channels for streaming data from the burst capable slaves on the DEBUGCELL. This data is streamed via PSIL through the UDMA and then to any slave interface in the system. The mapping of DEBUGCELL signals to PDMA channels is defined in the Peripheral DMA (PDMA) TRM chapter.