SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
This section describes the UFS external connections (environment).
Figure 12-214 shows the UFS I/O interface signals.
Table 12-301 describes the UFS I/O signals.
Module Pin | I/O(1) | Description |
---|---|---|
UFS0 | ||
RX_DP0 | I | UFS Lane0 RX Data Positive |
RX_DN0 | I | UFS Lane0 RX Data Negative |
TX_DP0 | O | UFS Lane0 TX Data Positive |
TX_DN0 | O | UFS Lane0 TX Data Negative |
RX_DP1 | I | UFS Lane1 RX Data Positive |
RX_DN1 | I | UFS Lane1 RX Data Negative |
TX_DP1 | O | UFS Lane1 TX Data Positive |
TX_DN1 | O | UFS Lane1 TX Data Negative |
REF_CLK | O | UFS Reference Clock Signal to Slave |
RSTn | O | UFS Reset Signal to Slave |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.