Product details


FET Internal Ron (Typ) (mOhm) 42 Vin (Min) (V) 2.7 Vin (Max) (V) 18 Vabsmax_cont (V) 20 Current limit (Min) (A) 0.6 Current limit (Max) (A) 5.2 Overcurrent response Current limiting UL recognition UL2367, UL60950 open-in-new Find other eFuses & hot swap controllers

Package | Pins | Size

WQFN (RVC) 20 12 mm² 3 x 4 open-in-new Find other eFuses & hot swap controllers


  • 2.7 V – 18 V Operating Voltage, 20 V (Max)
  • 42 mΩ RON (Typical)
  • 0.6 A to 5.3 A Adjustable Current Limit (±8%)
  • IMON Current Indicator Output (±8%)
  • 200 µA Operating IQ (Typical)
  • 95 µA DevSleep Mode IQ (Typical)
  • 15 µA Disabled IQ (Typical)
  • ±2% Overvoltage, Undervoltage Threshold
  • Reverse Current Blocking
  • 1 µs Reverse Voltage Shutoff
  • Programmable dVo/dt Control
  • Power Good and Fault Outputs
  • –40°C to 125°C Junction Temperature Range
  • UL 2367 Recognized
    • File No. 169910
    • RILIM ≥ 20 kΩ (4.81 A max)
  • UL60950 - Safe during Single Point Failure Test
    • Open/Short ILIM detection
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The TPS25940 eFuse Power Switch is a compact, feature rich power management device with a full suite of protection functions, including a low power DevSleep™ mode that supports compliance with the SATA™ Device Sleep standard. The wide operating range allows control of many popular DC bus voltages. Integrated back to back FETs provide bidirectional current control making the device well suited for systems with load side holdup energy that must not drain back to a failed supply bus.

Load, source and device protection are provided with many programmable features including overcurrent, dVo/dt ramp and overvoltage, undervoltage thresholds. For system status monitoring and downstream load control, the device provides PGOOD, FLT and precise current monitor output. Precise programmable undervoltage, overvoltage thresholds and the low IQ DevSleep mode simplify SSD power management design.

The TPS25940 monitors V(IN) and V(OUT) to provide true reverse current blocking when V(IN) < (V(OUT) - 10 mV). This function supports swift changeover to a boosted voltage energy storage element in systems where backup voltage is greater than bus voltage.

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NEW TPS25947 ACTIVE 2.7-V to 23-V, 28-mΩ, 5.5-A eFuse with integrated reverse polarity protection Improved performance and pricing in a smaller package

Technical documentation

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Type Title Date
* Data sheet TPS25940x 2.7 – 18V eFuse with True Reverse Blocking and DevSleep Support for SSDs datasheet (Rev. A) Mar. 26, 2015
Certificate TPS25940 CB Test Certificate IEC 62368-1 Jul. 08, 2021
Certificate TPS2594x UL Certificate of Compliance UL 2367 Apr. 10, 2020
Application note eFuse: Safety Certification and why it Matters Mar. 18, 2020
Certificate TPS25940 UL Certificate of Compliance IEC 62368-1 Jan. 17, 2020
E-book 11 Ways to Protect Your Power Path white paper Jul. 03, 2019
Application note Minimizing System Down-time with Smart eFuses Jun. 12, 2019
User guide TPS25940 Evaluation Module User's Guide (Rev. B) Jul. 09, 2018
Application note Basics of eFuses (Rev. A) Apr. 05, 2018
Application note Charging Super Capacitor With eFuse Aug. 08, 2017
Technical article How adding an eFuse will protect your brand’s reputation Jun. 21, 2017
Application note Power Multiplexing Using Load Switches and eFuses (Rev. A) Jun. 20, 2017
Application note Achieve 20-A Circuit Protection and Space Efficiency Using Paralleled eFuses Nov. 03, 2016
Technical article eFuses: clamping and cutoff and auto retry, oh my! – part 2/3 May 26, 2016
Technical article eFuses: clamping and cutoff and auto retry, oh my! – part 1/3 May 10, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

TPS25940x Evaluation Module
document-generic User guide

The TPS25940XEVM-635 is an eFuse (Current Limiter with DEVSLP) that operates from 2.7V to 18V, and have integrated back-to-back FETs with programmable under-voltage, over-voltage, reverse-voltage, over-current and in-rush current protection. It also includes analog current monitoring in a small (...)

  • 2.7V to 18V operating voltage range
  • Up to 5A Adjustable ILIMIT setting option using Jumpers
  • On board fault and power good LED’s
  • Linear output ramp (gate dV/dt control) option
  • On board test point access for all device level pins

Design tools & simulation

SLVMAB0C.ZIP (72 KB) - PSpice Model
SLVMAB1C.ZIP (72 KB) - PSpice Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SLVC571.ZIP (190 KB)

Reference designs

e-Fuse Power Switch with DevSleep SATA Interface
TIDA-00429 TPS25940A provides a dedicated DevSleep interface terminal (DEVSLP) to force the device in low power mode. The DEVSLP pin is compatible with standard hardware signals asserted from the host controller. When pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent (...)
document-generic Schematic document-generic User guide
Last Gasp Hold Up Energy Storage Solution
TIDA-00304 This solution stores and delivers "last gasp" energy for systems, such as SSDs, that require functionality for a short time after power loss in order to shut down in a controlled fashion. By storing holdup energy at higher than bus voltage the amount of capacitance can be reduced by up to 80 (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
WQFN (RVC) 20 View options

Ordering & quality

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