SPRUIU1 User guide

SPRUIU1D July 2020 – December 2024 DRA821U , DRA821U-Q1

12.3.2.6 OSPI Registers

This section describes OSPI Global Control registers, OSPI Configuration registers, and OSPI_ECC_AGGR registers.

3.2.6.1 OSPI Global Control Registers

Table 12-3921 lists the memory-mapped registers for the OSPI Global Control Registers. All register offset addresses not listed in Table 12-3921 should be considered as reserved locations and the register contents should not be modified.

The Global Control Registers region is accessed by setting the Region Select signal to 0 during the access. The address map for this region is as follows:

Table 12-3920 OSPI Global Control Instances

Instance	Base Address
MCU_FSS0_OSPI0_SS_CFG	4704 4000h

Table 12-3921 OSPI Global Control Registers

Offset	Acronym	Register Name	MCU_FSS0_OSPI0_SS_CFG Physical Address
0h	OSPI_PID	Revision register	4704 4000h
4h	OSPI_CTRL	Control register	4704 4004h
8h	OSPI_STAT	Status regsiter	4704 4008h
20h	OSPI_EOI	End of interrupt	4704 4020h

3.2.6.2 OSPI_PID Register (Offset = 0h) [reset = X]

OSPI_PID is shown in Figure 12-1977 and described in Table 12-3923.

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The Revision Register contains the major and minor revisions for the module.

Table 12-3922 OSPI_PID Instances

Instance	Physical Address
MCU_FSS0_OSPI0_SS_CFG	4704 4000h

Figure 12-1977 OSPI_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE_ID
R-1h		R-2h		R-874h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTL					MAJOR			CUSTOM		MINOR
R-Dh					R-1h			R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3923 OSPI_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	OSPI_PID register scheme
29-28	BU	R	2h	Business Unit: 10 = Processors
27-16	MODULE_ID	R	874h	Module ID
15-11	RTL	R	Dh	RTL revision. Will vary depending on release.
10-8	MAJOR	R	1h	Major revision
7-6	CUSTOM	R	0h	Custom
5-0	MINOR	R	0h	Minor revision

3.2.6.3 OSPI_CTRL Register (Offset = 4h) [reset = 0h]

OSPI_CTRL is shown in Figure 12-1978 and described in Table 12-3925.

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The Control Register contains general control bits for the OSPI.

Table 12-3924 OSPI_CTRL Instances

Instance	Physical Address
MCU_FSS0_OSPI0_SS_CFG	4704 4004h

Figure 12-1978 OSPI_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				PIPELINE_MODE_FLUSH	RESERVED
R-0h				R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3925 OSPI_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	PIPELINE_MODE_FLUSH	R/W	0h	1h = Flush Flash Controller FIFO by forcing data interface slave select signal low. 0h = Data interface slave select signal to Controller is 1.
2-0	RESERVED	R	0h	Reserved

3.2.6.4 OSPI_STAT Register (Offset = 8h) [reset = 0h]

OSPI_STAT is shown in Figure 12-1979 and described in Table 12-3927.

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The Status register provide general status bits for the OSPI.

Table 12-3926 OSPI_STAT Instances

Instance	Physical Address
MCU_FSS0_OSPI0_SS_CFG	4704 4008h

Figure 12-1979 OSPI_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						MEM_INIT_DONE	RESERVED
R-0h						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3927 OSPI_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	MEM_INIT_DONE	R	0h	0h = Memory initialization is in progress, 1h = Memory intialization is done.
0	RESERVED	R	0h	Reserved

3.2.6.5 OSPI_EOI Register (Offset = 20h) [reset = 0h]

OSPI_EOI is shown in Figure 12-1980 and described in Table 12-3929.

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End of Interrupt Register

The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.

Note:

Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.

Table 12-3928 OSPI_EOI Instances

Instance	Physical Address
MCU_FSS0_OSPI0_SS_CFG	4704 4020h

Figure 12-1980 OSPI_EOI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								EOI
R-0h																								W-0h

LEGEND: R = Read Only; W = Write Only; -n = value after reset

Table 12-3929 OSPI_EOI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	EOI	W	0h	Write with bit position of targetted interrupt. (that is Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt.

3.2.6.6 OSPI Module Configuration Registers

Table 12-3931 lists the memory-mapped registers for the OSPI Module Configuration registers. All register offset addresses not listed in Table 12-3931 should be considered as reserved locations and the register contents should not be modified.

Table 12-3930 OSPI Module Configuration Instances

Instance	Base Address
MCU_FSS0_OSPI0_CTRL	4704 0000h

Table 12-3931 OSPI Module Configuration Registers

Offset	Acronym	Register Name	MCU_FSS0_OSPI0_CTRL Physical Address
0h	OSPI_CONFIG_REG	OSPI configuration register	4704 0000h
4h	OSPI_DEV_INSTR_RD_CONFIG_REG	Read instruction configuration register	4704 0004h
8h	OSPI_DEV_INSTR_WR_CONFIG_REG	Write instruction configuration register	4704 0008h
Ch	OSPI_DEV_DELAY_REG	OSPI delay register	4704 000Ch
10h	OSPI_RD_DATA_CAPTURE_REG	Read data capture register	4704 0010h
14h	OSPI_DEV_SIZE_CONFIG_REG	Device size configuration register	4704 0014h
18h	OSPI_SRAM_PARTITION_CFG_REG	SRAM partition configuration register	4704 0018h
1Ch	OSPI_IND_AHB_ADDR_TRIGGER_REG	Indirect trigger address register	4704 001Ch
20h	OSPI_DMA_PERIPH_CONFIG_REG	DMA configuration register	4704 0020h
24h	OSPI_REMAP_ADDR_REG	Address remapping register	4704 0024h
28h	OSPI_MODE_BIT_CONFIG_REG	Mode bit configuration register	4704 0028h
2Ch	OSPI_SRAM_FILL_REG	SRAM fill level register	4704 002Ch
30h	OSPI_TX_THRESH_REG	TX threshold register	4704 0030h
34h	OSPI_RX_THRESH_REG	RX threshold register	4704 0034h
38h	OSPI_WRITE_COMPLETION_CTRL_REG	Write completion control register	4704 0038h
3Ch	OSPI_NO_OF_POLLS_BEF_EXP_REG	Polling expiration register	4704 003Ch
40h	OSPI_IRQ_STATUS_REG	Interrupt status register	4704 0040h
44h	OSPI_IRQ_MASK_REG	Interrupt mask register	4704 0044h
50h	OSPI_LOWER_WR_PROT_REG	Lower write protection register	4704 0050h
54h	OSPI_UPPER_WR_PROT_REG	Upper write protection register	4704 0054h
58h	OSPI_WR_PROT_CTRL_REG	Write protection control register	4704 0058h
60h	OSPI_INDIRECT_READ_XFER_CTRL_REG	Indirect read transfer control register	4704 0060h
64h	OSPI_INDIRECT_READ_XFER_WATERMARK_REG	Indirect read transfer watermark register	4704 0064h
68h	OSPI_INDIRECT_READ_XFER_START_REG	Indirect read transfer start address register	4704 0068h
6Ch	OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG	Indirect read transfer number bytes register	4704 006Ch
70h	OSPI_INDIRECT_WRITE_XFER_CTRL_REG	Indirect write transfer control register	4704 0070h
74h	OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG	Indirect write transfer watermark register	4704 0074h
78h	OSPI_INDIRECT_WRITE_XFER_START_REG	Indirect write transfer start address register	4704 0078h
7Ch	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG	Indirect write transfer number bytes register	4704 007Ch
80h	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG	Indirect trigger address range register	4704 0080h
8Ch	OSPI_FLASH_COMMAND_CTRL_MEM_REG	Flash command control memory register	4704 008Ch
90h	OSPI_FLASH_CMD_CTRL_REG	Flash command control register	4704 0090h
94h	OSPI_FLASH_CMD_ADDR_REG	Flash command address register	4704 0094h
A0h	OSPI_FLASH_RD_DATA_LOWER_REG	Flash command read data register (lower)	4704 00A0h
A4h	OSPI_FLASH_RD_DATA_UPPER_REG	Flash command read data register (upper)	4704 00A4h
A8h	OSPI_FLASH_WR_DATA_LOWER_REG	Flash command write data register (lower)	4704 00A8h
ACh	OSPI_FLASH_WR_DATA_UPPER_REG	Flash command write data register (upper)	4704 00ACh
B0h	OSPI_POLLING_FLASH_STATUS_REG	Polling Flash status register	4704 00B0h
B4h	OSPI_PHY_CONFIGURATION_REG	PHY configuration register	4704 00B4h
B8h	OSPI_PHY_MASTER_CONTROL_REG	PHY DLL master control register	4704 00B8h
BCh	OSPI_DLL_OBSERVABLE_LOWER_REG	DLL observable register (lower)	4704 00BCh
C0h	OSPI_DLL_OBSERVABLE_UPPER_REG	DLL observable register (upper)	4704 00C0h
E0h	OSPI_OPCODE_EXT_LOWER_REG	Opcode extension register (lower)	4704 00E0h
E4h	OSPI_OPCODE_EXT_UPPER_REG	Opcode extension register (upper)	4704 00E4h
FCh	OSPI_MODULE_ID_REG	Module ID register	4704 00FCh

3.2.6.7 OSPI_CONFIG_REG Register (Offset = 0h) [reset = 80780081h]

OSPI_CONFIG_REG is shown in Figure 12-1981 and described in Table 12-3933.

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OSPI Configuration Register

This register contains basic configuration fields of the controller.

Table 12-3932 OSPI_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0000h

Figure 12-1981 OSPI_CONFIG_REG Register

31	30	29	28	27	26	25	24
IDLE_FLD	DUAL_BYTE_OPCODE_EN_FLD	CRC_ENABLE_FLD	CONFIG_RESV2_FLD			PIPELINE_PHY_FLD	ENABLE_DTR_PROTOCOL_FLD
R-1h	R/W-0h	R/W-0h	R-0h			R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
ENABLE_AHB_DECODER_FLD	MSTR_BAUD_DIV_FLD				ENTER_XIP_MODE_IMM_FLD	ENTER_XIP_MODE_FLD	ENB_AHB_ADDR_REMAP_FLD
R/W-0h	R/W-Fh				R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
ENB_DMA_IF_FLD	WR_PROT_FLASH_FLD	PERIPH_CS_LINES_FLD				PERIPH_SEL_DEC_FLD	ENB_LEGACY_IP_MODE_FLD
R/W-0h	R/W-0h	R/W-0h				R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ENB_DIR_ACC_CTLR_FLD	RESET_CFG_FLD	RESET_PIN_FLD	HOLD_PIN_FLD	PHY_MODE_ENABLE_FLD	SEL_CLK_PHASE_FLD	SEL_CLK_POL_FLD	ENB_SPI_FLD
R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3933 OSPI_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	IDLE_FLD	R	1h	Serial interface and low level SPI pipeline is IDLE. This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal.
30	DUAL_BYTE_OPCODE_EN_FLD	R/W	0h	Dual-byte Opcode Mode enable bit. This bit is to be set in case the target Flash Device supports dual byte opcode. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device is configured to work in another SPI Mode. If enabled, the supplementing bytes are taken from OSPI_OPCODE_EXT_LOWER_REG and from OSPI_OPCODE_EXT_UPPER_REG.
29	CRC_ENABLE_FLD	R/W	0h	CRC enable bit. This bit is to be set in case the target Flash Device supports CRC. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode
28-26	CONFIG_RESV2_FLD	R	0h	Reserved
25	PIPELINE_PHY_FLD	R/W	0h	Pipeline PHY Mode enable. This bit is relevant only for configuration with PHY module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise.
24	ENABLE_DTR_PROTOCOL_FLD	R/W	0h	Enable DTR Protocol. This bit should be set if device is configured to work in DTR protocol.
23	ENABLE_AHB_DECODER_FLD	R/W	0h	Enable AHB Decoder. 0h = Active slave is selected based on the OSPI_CONFIG_REG[13:10] PERIPH_CS_LINES_FLD. 1h = Active slave is selected based on actual data interface address (the partition is calculated with respect to bits OSPI_DEV_SIZE_CONFIG_REG[28:21]).
22-19	MSTR_BAUD_DIV_FLD	R/W	Fh	Master mode baud rate divisor (2 to 32), OSPI baud rate = (master reference clock) / (baud rate devisor) Where baud rate devisor is: 0h = /2 1h = /4 2h = /6 3h = /8 4h = /10 5h = /12 6h = /14 7h = /16 8h = /18 … Fh = /32 Set this register up before enabling the OSPI controller.
18	ENTER_XIP_MODE_IMM_FLD	R/W	0h	Enter XIP Mode immediately. 0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value= 1h = Operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode [as per the contents of its non-volatile configuration register]. The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited.
17	ENTER_XIP_MODE_FLD	R/W	0h	Enter XIP Mode on next READ. 0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. 1h = If XIP is disabled, then setting to 1 will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited
16	ENB_AHB_ADDR_REMAP_FLD	R/W	0h	Enable Data Interface Address Remapping [Direct Access Mode Only] 1h = the incoming data interface address will be adapted and sent to the FLASH device as [address + N], where N is the value stored in the remap address register
15	ENB_DMA_IF_FLD	R/W	0h	Enable DMA Peripheral Interface. 0h = disable the DMA handshaking logic. 1h = enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. CAUTION: This bit should be left at 0 as feature is not supported.
14	WR_PROT_FLASH_FLD	R/W	0h	Write Protect Flash Pin. Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary.
13-10	PERIPH_CS_LINES_FLD	R/W	0h	Peripheral Chip Select Lines. If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0, ss[3:0] are output thus:
				ss[3-0] xxx0 xx01 x011 0111 1111	N_SS_OUT[3:0] 1110 1101 1011 0111 1111 [no peripheral selected]
				else ss[3-0] directly drives N_SS_OUT[3-0]
9	PERIPH_SEL_DEC_FLD	R/W	0h	Peripheral select decode. 0h = only 1 of 4 selects N_SS_OUT[3:0] is active, 1h = allow external 4-to-16 decode [N_SS_OUT = ss]
8	ENB_LEGACY_IP_MODE_FLD	R/W	0h	Legacy IP Mode Enable. 0h = Use Direct Access Controller/Indirect Access Controller 1h = Legacy Mode is enabled. In this mode, any write to the controller via the data interface is serialized and sent to the FLASH device. Any valid data read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, 4, 2 or 1 byte transfers are permitted and controlled.
7	ENB_DIR_ACC_CTLR_FLD	R/W	1h	Enable Direct Access Controller. 0h = Disable the Direct Access Controller once current transfer of the data word is complete. 1h = Enable the Direct Access Controller. When the Direct Access Controller and Indirect Access Controller are both disabled, all data requests are completed with an error response.
6	RESET_CFG_FLD	R/W	0h	RESET pin configuration. 0h = RESET feature on DQ3 pin of the device 1h = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output].
5	RESET_PIN_FLD	R/W	0h	Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature.
4	HOLD_PIN_FLD	R/W	0h	Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature.
3	PHY_MODE_ENABLE_FLD	R/W	0h	PHY mode enable. When enabled, the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module.
2	SEL_CLK_PHASE_FLD	R/W	0h	Select Clock Phase. Selects whether the clock is in an active or inactive phase outside the SPI word 0h = The SPI clock is active outside the word 1h = The SPI clock is inactive outside the word
1	SEL_CLK_POL_FLD	R/W	0h	Clock polarity outside SPI word. 0h = The SPI clock is quiescent low 1h = The SPI clock is quiescent high
0	ENB_SPI_FLD	R/W	1h	OSPI Enable. 0h = Disable the OSPI, once current transfer of the data word is complete. 1h = Enable the OSPI, when this bit is set to 0, all output enables are inactive and all pins are set to input mode.

3.2.6.8 OSPI_DEV_INSTR_RD_CONFIG_REG Register (Offset = 4h) [reset = 3h]

OSPI_DEV_INSTR_RD_CONFIG_REG is shown in Figure 12-1982 and described in Table 12-3935.

Return to Summary Table.

Device Read Instruction Configuration Register.

This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle.

Table 12-3934 OSPI_DEV_INSTR_RD_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0004h

Figure 12-1982 OSPI_DEV_INSTR_RD_CONFIG_REG Register

31	30	29	28	27	26	25	24
RD_INSTR_RESV5_FLD			DUMMY_RD_CLK_CYCLES_FLD
R-0h			R/W-0h

23	22	21	20	19	18	17	16
RD_INSTR_RESV4_FLD			MODE_BIT_ENABLE_FLD	RD_INSTR_RESV3_FLD		DATA_XFER_TYPE_EXT_MODE_FLD
R-0h			R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
RD_INSTR_RESV2_FLD		ADDR_XFER_TYPE_STD_MODE_FLD		RD_INSTR_RESV1_FLD	DDR_EN_FLD	INSTR_TYPE_FLD
R-0h		R/W-0h		R-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RD_OPCODE_NON_XIP_FLD
R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3935 OSPI_DEV_INSTR_RD_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RD_INSTR_RESV5_FLD	R	0h	Reserved
28-24	DUMMY_RD_CLK_CYCLES_FLD	R/W	0h	Dummy Read Clock Cycles. Number of dummy clock cycles required by device for read instruction.
23-21	RD_INSTR_RESV4_FLD	R	0h	Reserved
20	MODE_BIT_ENABLE_FLD	R/W	0h	Mode Bit Enable. Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.
19-18	RD_INSTR_RESV3_FLD	R	0h	Reserved
17-16	DATA_XFER_TYPE_EXT_MODE_FLD	R/W	0h	Data Transfer Type for Standard SPI modes. 0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Octal Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs
15-14	RD_INSTR_RESV2_FLD	R	0h	Reserved
13-12	ADDR_XFER_TYPE_STD_MODE_FLD	R/W	0h	Address Transfer Type for Standard SPI modes. 0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2, and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]
11	RD_INSTR_RESV1_FLD	R	0h	Reserved
10	DDR_EN_FLD	R/W	0h	DDR Enable. This is to inform that opcode from OSPI_DEV_INSTR_RD_CONFIG_REG[7-0] RD_OPCODE_NON_XIP_ FLD is compliant with one of the DDR READ commands.
9-8	INSTR_TYPE_FLD	R/W	0h	Instruction Type. 0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1h = Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2h = Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2, and DQ3] 3h = Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]]
7-0	RD_OPCODE_NON_XIP_FLD	R/W	3h	Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode

3.2.6.9 OSPI_DEV_INSTR_WR_CONFIG_REG Register (Offset = 8h) [reset = 2h]

OSPI_DEV_INSTR_WR_CONFIG_REG is shown in Figure 12-1983 and described in Table 12-3937.

Return to Summary Table.

Device Write Instruction Configuration Register.

This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle.

Table 12-3936 OSPI_DEV_INSTR_WR_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0008h

Figure 12-1983 OSPI_DEV_INSTR_WR_CONFIG_REG Register

31	30	29	28	27	26	25	24
WR_INSTR_RESV4_FLD			DUMMY_WR_CLK_CYCLES_FLD
R-0h			R/W-0h

23	22	21	20	19	18	17	16
WR_INSTR_RESV3_FLD						DATA_XFER_TYPE_EXT_MODE_FLD
R-0h						R/W-0h

15	14	13	12	11	10	9	8
WR_INSTR_RESV2_FLD		ADDR_XFER_TYPE_STD_MODE_FLD		WR_INSTR_RESV1_FLD			WEL_DIS_FLD
R-0h		R/W-0h		R-0h			R/W-0h

7	6	5	4	3	2	1	0
WR_OPCODE_FLD
R/W-2h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3937 OSPI_DEV_INSTR_WR_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	WR_INSTR_RESV4_FLD	R	0h	Reserved
28-24	DUMMY_WR_CLK_CYCLES_FLD	R/W	0h	Dummy Write Clock Cycles. Number of dummy clock cycles required by device for write instruction
23-18	WR_INSTR_RESV3_FLD	R	0h	Reserved
17-16	DATA_XFER_TYPE_EXT_MODE_FLD	R/W	0h	Data Transfer Type for Standard SPI modes. 0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Octal Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs
15-14	WR_INSTR_RESV2_FLD	R	0h	Reserved
13-12	ADDR_XFER_TYPE_STD_MODE_FLD	R/W	0h	Address Transfer Type for Standard SPI modes. 0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2. and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]
11-9	WR_INSTR_RESV1_FLD	R	0h	Reserved
8	WEL_DIS_FLD	R/W	0h	WEL Disable. This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC.
7-0	WR_OPCODE_FLD	R/W	2h	Write Opcode

3.2.6.10 OSPI_DEV_DELAY_REG Register (Offset = Ch) [reset = 0h]

OSPI_DEV_DELAY_REG is shown in Figure 12-1984 and described in Table 12-3939.

Return to Summary Table.

OSPI Device Delay Register. This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the OSPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.

This register should be setup while the controller is idle.

Table 12-3938 OSPI_DEV_DELAY_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 000Ch

Figure 12-1984 OSPI_DEV_DELAY_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
D_NSS_FLD								D_BTWN_FLD
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D_AFTER_FLD								D_INIT_FLD
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3939 OSPI_DEV_DELAY_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	D_NSS_FLD	R/W	0h	Clock Delay for Chip Select Deassert. Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period.
23-16	D_BTWN_FLD	R/W	0h	Clock Delay for Chip Select Deactivation. Delay in master reference clocks between one chip select being de-activated and the activation of another This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty.
15-8	D_AFTER_FLD	R/W	0h	Clock Delay for Last Transaction Bit. Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out] By default, the chip select will be deasserted on the cycle following the completion of the current transaction.
7-0	D_INIT_FLD	R/W	0h	Clock Delay with N_SS_OUT. Delay in master reference clocks between setting n_ss_out low and first bit transfer.

3.2.6.11 OSPI_RD_DATA_CAPTURE_REG Register (Offset = 10h) [reset = 1h]

OSPI_RD_DATA_CAPTURE_REG is shown in Figure 12-1985 and described in Table 12-3941.

Return to Summary Table.

Read Data Capture Register.

This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle.

Table 12-3940 OSPI_RD_DATA_CAPTURE_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0010h

Figure 12-1985 OSPI_RD_DATA_CAPTURE_REG Register

31	30	29	28	27	26	25	24
RD_DATA_RESV3_FLD
R-0h

23	22	21	20	19	18	17	16
RD_DATA_RESV3_FLD				DDR_READ_DELAY_FLD
R-0h				R/W-0h

15	14	13	12	11	10	9	8
RD_DATA_RESV2_FLD							DQS_ENABLE_FLD
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RD_DATA_RESV1_FLD		SAMPLE_EDGE_SEL_FLD	DELAY_FLD				BYPASS_FLD
R-0h		R/W-0h	R/W-0h				R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3941 OSPI_RD_DATA_CAPTURE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RD_DATA_RESV3_FLD	R	0h	Reserved
19-16	DDR_READ_DELAY_FLD	R/W	0h	DDR read delay. Delay the transmitted data by the programmed number of RCLK cycles. This field is only relevant when DDR Read Command is executed. Otherwise can be ignored.
15-9	RD_DATA_RESV2_FLD	R	0h	Reserved
8	DQS_ENABLE_FLD	R/W	0h	DQS enable bit. If enabled, signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated RCLK.
7-6	RD_DATA_RESV1_FLD	R	0h	Reserved
5	SAMPLE_EDGE_SEL_FLD	R/W	0h	Sample edge selection. Choose edge on which data outputs from flash memory will be sampled. 0h = Data outputs from flash memory are sampled on falling edge of the RCLK. 1h = Data outputs from flash memory are sampled on rising edge of the RCLK.
4-1	DELAY_FLD	R/W	0h	Read Delay. Delay the read data capturing logic by the programmed number of RCLK cycles.
0	BYPASS_FLD	R/W	1h	Bypass. Bypass the adapted loopback clock circuit.

3.2.6.12 OSPI_DEV_SIZE_CONFIG_REG Register (Offset = 14h) [reset = 00101002h]

OSPI_DEV_SIZE_CONFIG_REG is shown in Figure 12-1986 and described in Table 12-3943.

Return to Summary Table.

Device Size Configuration Register.

This register allows to define the memory organization of using Flash Devices. This register should be setup while the controller is idle.

Table 12-3942 OSPI_DEV_SIZE_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0014h

Figure 12-1986 OSPI_DEV_SIZE_CONFIG_REG Register

31	30	29	28	27	26	25	24
DEV_SIZE_RESV_FLD			MEM_SIZE_ON_CS3_FLD		MEM_SIZE_ON_CS2_FLD		MEM_SIZE_ON_CS1_FLD
R-0h			R/W-0h		R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
MEM_SIZE_ON_CS1_FLD	MEM_SIZE_ON_CS0_FLD		BYTES_PER_SUBSECTOR_FLD
R/W-0h	R/W-0h		R/W-10h

15	14	13	12	11	10	9	8
BYTES_PER_DEVICE_PAGE_FLD
R/W-100h

7	6	5	4	3	2	1	0
BYTES_PER_DEVICE_PAGE_FLD				NUM_ADDR_BYTES_FLD
R/W-100h				R/W-2h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3943 OSPI_DEV_SIZE_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	DEV_SIZE_RESV_FLD	R	0h	Reserved
28-27	MEM_SIZE_ON_CS3_FLD	R/W	0h	Size of Flash Device connected to CS[3] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb
26-25	MEM_SIZE_ON_CS2_FLD	R/W	0h	Size of Flash Device connected to CS[2] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb
24-23	MEM_SIZE_ON_CS1_FLD	R/W	0h	Size of Flash Device connected to CS[1] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb
22-21	MEM_SIZE_ON_CS0_FLD	R/W	0h	Size of Flash Device connected to CS[0] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb
20-16	BYTES_PER_SUBSECTOR_FLD	R/W	10h	Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number. 0 = 1 byte h = 2 bytes 3 = 8 bytes ... 16 = 65535 bytes, etc.
15-4	BYTES_PER_DEVICE_PAGE_FLD	R/W	100h	Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries.
3-0	NUM_ADDR_BYTES_FLD	R/W	2h	Number of address bytes. A value of 0 indicates 1 byte.

3.2.6.13 OSPI_SRAM_PARTITION_CFG_REG Register (Offset = 18h) [reset = 80h]

OSPI_SRAM_PARTITION_CFG_REG is shown in Figure 12-1987 and described in Table 12-3945.

Return to Summary Table.

SRAM Partition Configuration Register.

Table 12-3944 OSPI_SRAM_PARTITION_CFG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0018h

Figure 12-1987 OSPI_SRAM_PARTITION_CFG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRAM_PARTITION_RESV_FLD																								ADDR_FLD
R-0h																								R/W-80h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3945 OSPI_SRAM_PARTITION_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	SRAM_PARTITION_RESV_FLD	R	0h	Reserved
7-0	ADDR_FLD	R/W	80h	Indirect Read Partition Size. Defines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM.

3.2.6.14 OSPI_IND_AHB_ADDR_TRIGGER_REG Register (Offset = 1Ch) [reset = 0h]

OSPI_IND_AHB_ADDR_TRIGGER_REG is shown in Figure 12-1988 and described in Table 12-3947.

Return to Summary Table.

Indirect AHB Address Trigger Register.

This register allowsto define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle.

Table 12-3946 OSPI_IND_AHB_ADDR_TRIGGER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 001Ch

Figure 12-1988 OSPI_IND_AHB_ADDR_TRIGGER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3947 OSPI_IND_AHB_ADDR_TRIGGER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_FLD	R/W	0h	Indirect Trigger Address. This is the base address used by the data interface. When the incoming data read/write access address matches a range of addresses from this trigger address to the trigger address + [configured range in OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG], then the data request is completed by fetching data from the Indirect Controllers SRAM.

3.2.6.15 OSPI_DMA_PERIPH_CONFIG_REG Register (Offset = 20h) [reset = 0h]

OSPI_DMA_PERIPH_CONFIG_REG is shown in Figure 12-1989 and described in Table 12-3949.

Return to Summary Table.

DMA Peripheral Configuration Register.

This register allows to define the parameters of DMA peripheral controller. This register should be setup while the controller is idle.

Note: Reserved. This feature is not supported.

Table 12-3948 OSPI_DMA_PERIPH_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0020h

Figure 12-1989 OSPI_DMA_PERIPH_CONFIG_REG Register

31	30	29	28	27	26	25	24
DMA_PERIPH_RESV2_FLD
R-0h

23	22	21	20	19	18	17	16
DMA_PERIPH_RESV2_FLD
R-0h

15	14	13	12	11	10	9	8
DMA_PERIPH_RESV2_FLD				NUM_BURST_REQ_BYTES_FLD
R-0h				R/W-0h

7	6	5	4	3	2	1	0
DMA_PERIPH_RESV1_FLD				NUM_SINGLE_REQ_BYTES_FLD
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3949 OSPI_DMA_PERIPH_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	DMA_PERIPH_RESV2_FLD	R	0h	Reserved
11-8	NUM_BURST_REQ_BYTES_FLD	R/W	0h	Number of Burst Bytes. Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**[value in this register] which will simplify implementation.
7-4	DMA_PERIPH_RESV1_FLD	R	0h	Reserved
3-0	NUM_SINGLE_REQ_BYTES_FLD	R/W	0h	Number of Single Bytes. Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**[value in this register] which will simplify implementation.

3.2.6.16 OSPI_REMAP_ADDR_REG Register (Offset = 24h) [reset = 0h]

OSPI_REMAP_ADDR_REG is shown in Figure 12-1990 and described in Table 12-3951.

Return to Summary Table.

Remap Address Register.

This register allows to define the address offset for DAC accesses. This register should be setup while the controller is idle.

Table 12-3950 OSPI_REMAP_ADDR_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0024h

Figure 12-1990 OSPI_REMAP_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VALUE_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3951 OSPI_REMAP_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VALUE_FLD	R/W	0h	This register is used to remap an incoming data address to a different address used by the FLASH device.

3.2.6.17 OSPI_MODE_BIT_CONFIG_REG Register (Offset = 28h) [reset = 200h]

OSPI_MODE_BIT_CONFIG_REG is shown in Figure 12-1991 and described in Table 12-3953.

Return to Summary Table.

Mode Bit Configuration Register.

This register allows to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle.

Table 12-3952 OSPI_MODE_BIT_CONFIG_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0028h

Figure 12-1991 OSPI_MODE_BIT_CONFIG_REG Register

31	30	29	28	27	26	25	24
RX_CRC_DATA_LOW_FLD
R-0h

23	22	21	20	19	18	17	16
RX_CRC_DATA_UP_FLD
R-0h

15	14	13	12	11	10	9	8
CRC_OUT_ENABLE_FLD	MODE_BIT_RESV1_FLD				CHUNK_SIZE_FLD
R/W-0h	R-0h				R/W-2h

7	6	5	4	3	2	1	0
MODE_FLD
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3953 OSPI_MODE_BIT_CONFIG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RX_CRC_DATA_LOW_FLD	R	0h	RX CRC data [lower]. The first CRC byte returned after RX data chunk.
23-16	RX_CRC_DATA_UP_FLD	R	0h	RX CRC data [upper]. The second CRC byte returned after RX data chunk.
15	CRC_OUT_ENABLE_FLD	R/W	0h	CRC# output enable bit. When enabled, the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly.
14-11	MODE_BIT_RESV1_FLD	R	0h	Reserved
10-8	CHUNK_SIZE_FLD	R/W	2h	It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers. 0h = 4 bytes 1h = 8 bytes 2h = 16 bytes 3h = 32 bytes 4h = 64 bytes 5h = 128 bytes 6h = 256 bytes 7h = 512 bytes
7-0	MODE_FLD	R/W	0h	These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled.

3.2.6.18 OSPI_SRAM_FILL_REG Register (Offset = 2Ch) [reset = 0h]

OSPI_SRAM_FILL_REG is shown in Figure 12-1992 and described in Table 12-3955.

Return to Summary Table.

SRAM Fill Register.

This register keeps the values of current fill levels of both SRAM partitions.

Table 12-3954 OSPI_SRAM_FILL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 002Ch

Figure 12-1992 OSPI_SRAM_FILL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SRAM_FILL_INDAC_WRITE_FLD
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRAM_FILL_INDAC_READ_FLD
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3955 OSPI_SRAM_FILL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SRAM_FILL_INDAC_WRITE_FLD	R	0h	SRAM Fill Level [Indirect Write Partition]. Identifies the current fill level of the SRAM Indirect Write partition.
15-0	SRAM_FILL_INDAC_READ_FLD	R	0h	SRAM Fill Level [Indirect Read Partition]. Identifies the current fill level of the SRAM Indirect Read partition.

3.2.6.19 OSPI_TX_THRESH_REG Register (Offset = 30h) [reset = 1h]

OSPI_TX_THRESH_REG is shown in Figure 12-1993 and described in Table 12-3957.

Return to Summary Table.

TX Threshold Register.

This register allows to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle.

Table 12-3956 OSPI_TX_THRESH_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0030h

Figure 12-1993 OSPI_TX_THRESH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TX_THRESH_RESV_FLD
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TX_THRESH_RESV_FLD											LEVEL_FLD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3957 OSPI_TX_THRESH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	TX_THRESH_RESV_FLD	R	0h	Reserved
4-0	LEVEL_FLD	R/W	1h	Defines the level at which the small TX FIFO not full interrupt is generated

3.2.6.20 OSPI_RX_THRESH_REG Register (Offset = 34h) [reset = 1h]

OSPI_RX_THRESH_REG is shown in Figure 12-1994 and described in Table 12-3959.

Return to Summary Table.

RX Threshold Register.

This register allows to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle.

Table 12-3958 OSPI_RX_THRESH_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0034h

Figure 12-1994 OSPI_RX_THRESH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RX_THRESH_RESV_FLD
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_THRESH_RESV_FLD											LEVEL_FLD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3959 OSPI_RX_THRESH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RX_THRESH_RESV_FLD	R	0h	Reserved
4-0	LEVEL_FLD	R/W	1h	Defines the level at which the small RX FIFO not empty interrupt is generated.

3.2.6.21 OSPI_WRITE_COMPLETION_CTRL_REG Register (Offset = 38h) [reset = 00010005h]

OSPI_WRITE_COMPLETION_CTRL_REG is shown in Figure 12-1995 and described in Table 12-3961.

Return to Summary Table.

Write Completion Control Register. This register defines how the controller will poll the device following a write transfer.

Table 12-3960 OSPI_WRITE_COMPLETION_CTRL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0038h

Figure 12-1995 OSPI_WRITE_COMPLETION_CTRL_REG Register

31	30	29	28	27	26	25	24
POLL_REP_DELAY_FLD
R/W-0h

23	22	21	20	19	18	17	16
POLL_COUNT_FLD
R/W-1h

15	14	13	12	11	10	9	8
ENABLE_POLLING_EXP_FLD	DISABLE_POLLING_FLD	POLLING_POLARITY_FLD	WR_COMP_CTRL_RESV1_FLD		POLLING_BIT_INDEX_FLD
R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h

7	6	5	4	3	2	1	0
OPCODE_FLD
R/W-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3961 OSPI_WRITE_COMPLETION_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	POLL_REP_DELAY_FLD	R/W	0h	Polling repetition delay. Defines additional delay for maintain Chip Select de-asserted during auto-polling phase.
23-16	POLL_COUNT_FLD	R/W	1h	Polling count. Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register. The poll_count_fld in Write Completion Control register should always be set with values greater or eaqual to 3 (>=3).
15	ENABLE_POLLING_EXP_FLD	R/W	0h	Enable polling expiration. 1h = enabling auto-polling expiration in OSPI_NO_OF_POLLS_BEF_EXP_REG.
14	DISABLE_POLLING_FLD	R/W	0h	Disable polling. This switches off the automatic polling function.
13	POLLING_POLARITY_FLD	R/W	0h	Polling polarity. Defines the polling polarity. 0h = The write transfer to the device will be complete if the polled bit is equal to 0. 1h = The write transfer to the device will be complete if the polled bit is equal to 1.
12-11	WR_COMP_CTRL_RESV1_FLD	R	0h	Reserved
10-8	POLLING_BIT_INDEX_FLD	R/W	0h	Polling bit index. Defines the bit index that should be polled. 0h = bit 0 of the returned data will be polled for. 1h = bit 1 of the returned data will be polled for. 2h = bit 2 of the returned data will be polled for. ... 7h = bit 7 of the returned data will be polled for.
7-0	OPCODE_FLD	R/W	5h	Polling opcode. Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default, this will poll the standard device STATUS register using opcode 0x05.

3.2.6.22 OSPI_NO_OF_POLLS_BEF_EXP_REG Register (Offset = 3Ch) [reset = FFFFFFFFh]

OSPI_NO_OF_POLLS_BEF_EXP_REG is shown in Figure 12-1996 and described in Table 12-3963.

Return to Summary Table.

Polling Expiration Register.

This register defines maximum number of poll cycles. If the expected value of the bit being polled is not gotten after number defined in this register, the auto-polling is done on the next phase.

Table 12-3962 OSPI_NO_OF_POLLS_BEF_EXP_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 003Ch

Figure 12-1996 OSPI_NO_OF_POLLS_BEF_EXP_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NO_OF_POLLS_BEF_EXP_FLD
R/W-FFFFFFFFh

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3963 OSPI_NO_OF_POLLS_BEF_EXP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	NO_OF_POLLS_BEF_EXP_FLD	R/W	FFFFFFFFh	Defines the numbers of poll cycles after which auto-polling phase terminates and polling expiration interrupt is generated.

3.2.6.23 OSPI_IRQ_STATUS_REG Register (Offset = 40h) [reset = 0h]

OSPI_IRQ_STATUS_REG is shown in Figure 12-1997 and described in Table 12-3965.

Return to Summary Table.

Interrupt Status Register. The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 through 10 are only valid when legacy SPI mode is active.

Table 12-3964 OSPI_IRQ_STATUS_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0040h

Figure 12-1997 OSPI_IRQ_STATUS_REG Register

31	30	29	28	27	26	25	24
IRQ_STAT_RESV_FLD
R-0h

23	22	21	20	19	18	17	16
IRQ_STAT_RESV_FLD				ECC_FAIL_FLD	TX_CRC_CHUNK_BRK_FLD	RX_CRC_DATA_VAL_FLD	RX_CRC_DATA_ERR_FLD
R/W1C-0h				R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

15	14	13	12	11	10	9	8
IRQ_STAT_RESV1_FLD	STIG_REQ_INT_FLD	POLL_EXP_INT_FLD	INDRD_SRAM_FULL_FLD	RX_FIFO_FULL_FLD	RX_FIFO_NOT_EMPTY_FLD	TX_FIFO_FULL_FLD	TX_FIFO_NOT_FULL_FLD
R-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

7	6	5	4	3	2	1	0
RECV_OVERFLOW_FLD	INDIRECT_XFER_LEVEL_BREACH_FLD	ILLEGAL_ACCESS_DET_FLD	PROT_WR_ATTEMPT_FLD	INDIRECT_READ_REJECT_FLD	INDIRECT_OP_DONE_FLD	UNDERFLOW_DET_FLD	MODE_M_FAIL_FLD
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3965 OSPI_IRQ_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	IRQ_STAT_RESV_FLD	R	0h	Reserved
19	ECC_FAIL_FLD	R/W1C	0h	ECC failure. This interrupt informs the system that Flash Device reported ECC error.
18	TX_CRC_CHUNK_BRK_FLD	R/W1C	0h	TX CRC chunk was broken. This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk.
17	RX_CRC_DATA_VAL_FLD	R/W1C	0h	RX CRC data valid. New RX CRC data was captured from Flash Device.
16	RX_CRC_DATA_ERR_FLD	R/W1C	0h	RX CRC data error. CRC data from Flash Device does not correspond to the one dynamically calculated by the controller
15	IRQ_STAT_RESV1_FLD	R	0h	Reserved
14	STIG_REQ_INT_FLD	R/W1C	0h	The controller is ready for getting another STIG request.
13	POLL_EXP_INT_FLD	R/W1C	0h	The maximum number of programmed polls cycles is expired.
12	INDRD_SRAM_FULL_FLD	R/W1C	0h	Indirect Read Partition overflow. Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation.
11	RX_FIFO_FULL_FLD	R/W1C	0h	Small RX FIFO full. Current FIFO status can be ignored in non-SPI legacy mode. 0h = FIFO is not full 1h = FIFO is full
10	RX_FIFO_NOT_EMPTY_FLD	R/W1C	0h	Small RX FIFO not empty. Current FIFO status can be ignored in non-SPI legacy mode. 0h = FIFO has less than RX THRESHOLD entries. 1h = FIFO has >= THRESHOLD entries.
9	TX_FIFO_FULL_FLD	R/W1C	0h	Small TX FIFO full. Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO is not full 1h = FIFO is full
8	TX_FIFO_NOT_FULL_FLD	R/W1C	0h	Small TX FIFO not full. Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO has >= THRESHOLD entries. 1h = FIFO has less than THRESHOLD entries.
7	RECV_OVERFLOW_FLD	R/W1C	0h	Receive Overflow. This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0h = no overflow has been detected. 1h = an overflow has occurred.
6	INDIRECT_XFER_LEVEL_BREACH_FLD	R/W1C	0h	Indirect Transfer Watermark Level Breached.
5	ILLEGAL_ACCESS_DET_FLD	R/W1C	0h	Illegal AHB access has been detected AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger.
4	PROT_WR_ATTEMPT_FLD	R/W1C	0h	Write to protected area was attempted and rejected.
3	INDIRECT_READ_REJECT_FLD	R/W1C	0h	Indirect operation was requested but could not be accepted. Two indirect operations already in storage.
2	INDIRECT_OP_DONE_FLD	R/W1C	0h	Indirect Operation Complete: Controller has completed last triggered indirect operation.
1	UNDERFLOW_DET_FLD	R/W1C	0h	Underflow Detected: 0h = no underflow has been detected 1h = underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation. This bit is reset only by a system reset and cleared only when the register is read.
0	MODE_M_FAIL_FLD	R/W1C	0h	Mode M Failure. Mode M failure indicates the voltage on pin N_SS_IN is inconsistent with the SPI mode. Set =1 if N_SS_IN is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is: Read 0h = no mode fault has been detected. Read 1h = a mode fault has occurred.

3.2.6.24 OSPI_IRQ_MASK_REG Register (Offset = 44h) [reset = 0h]

OSPI_IRQ_MASK_REG is shown in Figure 12-1998 and described in Table 12-3967.

Return to Summary Table.

Interrupt Mask Register.

This register allows the user to mask/unmask particular interrupt sources. This register should be setup while the controller is idle.

0h = the interrupt for the corresponding interrupt status register bit is disabled.
1h = the interrupt for the corresponding interrupt status register bit is enabled.

Table 12-3966 OSPI_IRQ_MASK_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0044h

Figure 12-1998 OSPI_IRQ_MASK_REG Register

31	30	29	28	27	26	25	24
IRQ_MASK_RESV_FLD
R-0h

23	22	21	20	19	18	17	16
IRQ_MASK_RESV_FLD				ECC_FAIL_MASK_FLD	TX_CRC_CHUNK_BRK_MASK_FLD	RX_CRC_DATA_VAL_MASK_FLD	RX_CRC_DATA_ERR_MASK_FLD
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
IRQ_MASK_RESV1_FLD	STIG_REQ_MASK_FLD	POLL_EXP_INT_MASK_FLD	INDRD_SRAM_FULL_MASK_FLD	RX_FIFO_FULL_MASK_FLD	RX_FIFO_NOT_EMPTY_MASK_FLD	TX_FIFO_FULL_MASK_FLD	TX_FIFO_NOT_FULL_MASK_FLD
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RECV_OVERFLOW_MASK_FLD	INDIRECT_XFER_LEVEL_BREACH_MASK_FLD	ILLEGAL_ACCESS_DET_MASK_FLD	PROT_WR_ATTEMPT_MASK_FLD	INDIRECT_READ_REJECT_MASK_FLD	INDIRECT_OP_DONE_MASK_FLD	UNDERFLOW_DET_MASK_FLD	MODE_M_FAIL_MASK_FLD
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3967 OSPI_IRQ_MASK_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	IRQ_MASK_RESV_FLD	R	0h	Reserved
19	ECC_FAIL_MASK_FLD	R/W	0h	ECC failure Mask
18	TX_CRC_CHUNK_BRK_MASK_FLD	R/W	0h	TX CRC chunk was broken Mask
17	RX_CRC_DATA_VAL_MASK_FLD	R/W	0h	RX CRC data valid Mask
16	RX_CRC_DATA_ERR_MASK_FLD	R/W	0h	RX CRC data error Mask
15	IRQ_MASK_RESV1_FLD	R	0h	Reserved
14	STIG_REQ_MASK_FLD	R/W	0h	STIG request completion Mask
13	POLL_EXP_INT_MASK_FLD	R/W	0h	Polling expiration detected Mask
12	INDRD_SRAM_FULL_MASK_FLD	R/W	0h	Indirect Read Partition overflow mask
11	RX_FIFO_FULL_MASK_FLD	R/W	0h	Small RX FIFO full Mask
10	RX_FIFO_NOT_EMPTY_MASK_FLD	R/W	0h	Small RX FIFO not empty Mask
9	TX_FIFO_FULL_MASK_FLD	R/W	0h	Small TX FIFO full Mask
8	TX_FIFO_NOT_FULL_MASK_FLD	R/W	0h	Small TX FIFO not full Mask
7	RECV_OVERFLOW_MASK_FLD	R/W	0h	Receive Overflow Mask
6	INDIRECT_XFER_LEVEL_BREACH_MASK_FLD	R/W	0h	Transfer Watermark Breach Mask
5	ILLEGAL_ACCESS_DET_MASK_FLD	R/W	0h	Illegal Access Detected Mask
4	PROT_WR_ATTEMPT_MASK_FLD	R/W	0h	Protected Area Write Attempt Mask
3	INDIRECT_READ_REJECT_MASK_FLD	R/W	0h	Indirect Read Reject Mask
2	INDIRECT_OP_DONE_MASK_FLD	R/W	0h	Indirect Complete Mask
1	UNDERFLOW_DET_MASK_FLD	R/W	0h	Underflow Detected Mask
0	MODE_M_FAIL_MASK_FLD	R/W	0h	Mode M Failure Mask

3.2.6.25 OSPI_LOWER_WR_PROT_REG Register (Offset = 50h) [reset = 0h]

OSPI_LOWER_WR_PROT_REG is shown in Figure 12-1999 and described in Table 12-3969.

Return to Summary Table.

Lower Write Protection Register.

This register allows to define lower boundary of the write protection area. This register should be setup while the controller is idle.

Table 12-3968 OSPI_LOWER_WR_PROT_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0050h

Figure 12-1999 OSPI_LOWER_WR_PROT_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SUBSECTOR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3969 OSPI_LOWER_WR_PROT_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-0

SUBSECTOR_FLD

R/W

Lower Block Number.

The block number that defines the lower block in the range of blocks that is to be locked from writing.
The definition of a block in terms of number of bytes is programmable via the OSPI_DEV_SIZE_CONFIG_REG register.

3.2.6.26 OSPI_UPPER_WR_PROT_REG Register (Offset = 54h) [reset = 0h]

OSPI_UPPER_WR_PROT_REG is shown in Figure 12-2000 and described in Table 12-3971.

Return to Summary Table.

Upper Write Protection Register.

This register allows to define upper boundary of the write protection area. This register should be setup while the controller is idle.

Table 12-3970 OSPI_UPPER_WR_PROT_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0054h

Figure 12-2000 OSPI_UPPER_WR_PROT_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SUBSECTOR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3971 OSPI_UPPER_WR_PROT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	SUBSECTOR_FLD	R/W	0h	Lower Block Number. The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the OSPI_DEV_SIZE_CONFIG_REG register.

3.2.6.27 OSPI_WR_PROT_CTRL_REG Register (Offset = 58h) [reset = 0h]

OSPI_WR_PROT_CTRL_REG is shown in Figure 12-2001 and described in Table 12-3973.

Return to Summary Table.

Write Protection Control Register.

This register allows to define the configuration of write protection settings. This register should be setup while the controller is idle.

Table 12-3972 OSPI_WR_PROT_CTRL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0058h

Figure 12-2001 OSPI_WR_PROT_CTRL_REG Register

31	30	29	28	27	26	25	24
WR_PROT_CTRL_RESV_FLD
R-0h

23	22	21	20	19	18	17	16
WR_PROT_CTRL_RESV_FLD
R-0h

15	14	13	12	11	10	9	8
WR_PROT_CTRL_RESV_FLD
R-0h

7	6	5	4	3	2	1	0
WR_PROT_CTRL_RESV_FLD						ENB_FLD	INV_FLD
R-0h						R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3973 OSPI_WR_PROT_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	WR_PROT_CTRL_RESV_FLD	R	0h	Reserved
1	ENB_FLD	R/W	0h	Write Protection Enable Bit. 0h = the protection region is disabled. 1h = any data write access with an address within the protection region defined in the lower and upper write protection registers is rejected. A data error response is generated and an interrupt source triggered.
0	INV_FLD	R/W	0h	Write Protection Inversion Bit. 0h = the protection region defined in the lower and upper write protection registers is the region that the system is not permitted to write to. 1h = the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to.

3.2.6.28 OSPI_INDIRECT_READ_XFER_CTRL_REG Register (Offset = 60h) [reset = 0h]

OSPI_INDIRECT_READ_XFER_CTRL_REG is shown in Figure 12-2002 and described in Table 12-3975.

Return to Summary Table.

Indirect Read Transfer Control Register.

This register allows control of the Indirect Read Transfer logic.

Table 12-3974 OSPI_INDIRECT_READ_XFER_CTRL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0060h

Figure 12-2002 OSPI_INDIRECT_READ_XFER_CTRL_REG Register

31	30	29	28	27	26	25	24
INDIR_RD_XFER_RESV_FLD
R-0h

23	22	21	20	19	18	17	16
INDIR_RD_XFER_RESV_FLD
R-0h

15	14	13	12	11	10	9	8
INDIR_RD_XFER_RESV_FLD
R-0h

7	6	5	4	3	2	1	0
NUM_IND_OPS_DONE_FLD		IND_OPS_DONE_STATUS_FLD	RD_QUEUED_FLD	SRAM_FULL_FLD	RD_STATUS_FLD	CANCEL_FLD	START_FLD
R-0h		R/W1C-0h	R-0h	R/W1C-0h	R-0h	W-0h	W-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; W = Write Only; -n = value after reset

Table 12-3975 OSPI_INDIRECT_READ_XFER_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	INDIR_RD_XFER_RESV_FLD	R	0h	Reserved
7-6	NUM_IND_OPS_DONE_FLD	R	0h	This field contains the number of indirect operations which have been completed. This is used in conjunction with the OSPI_INDIRECT_READ_XFER_CTRL_REG[5] IND_OPS_DONE_STATUS_FLD It is incremented by hardware when an indirect operation has completed. Write a 1 to OSPI_INDIRECT_READ_XFER_CTRL_REG[5] IND_OPS_DONE_STATUS_FLD to decrement it.
5	IND_OPS_DONE_STATUS_FLD	R/W1C	0h	Indirect Completion Status. This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.
4	RD_QUEUED_FLD	R	0h	Queued Indirect Read Operations. Two indirect read operations have been queued.
3	SRAM_FULL_FLD	R/W1C	0h	SRAM Full. SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it indirect operation [status].
2	RD_STATUS_FLD	R	0h	Indirect Read Status. Indirect read operation in progress [status].
1	CANCEL_FLD	W	0h	Cancel Indirect Read. Writing a 1 to this bit will cancel all ongoing indirect read operations.
0	START_FLD	W	0h	Start Indirect Read. Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation.

3.2.6.29 OSPI_INDIRECT_READ_XFER_WATERMARK_REG Register (Offset = 64h) [reset = 0h]

OSPI_INDIRECT_READ_XFER_WATERMARK_REG is shown in Figure 12-2003 and described in Table 12-3977.

Return to Summary Table.

Indirect Read Transfer Watermark Register.

This register allows to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered.

Note:

Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.

Table 12-3976 OSPI_INDIRECT_READ_XFER_WATERMARK_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0064h

Figure 12-2003 OSPI_INDIRECT_READ_XFER_WATERMARK_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LEVEL_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3977 OSPI_INDIRECT_READ_XFER_WATERMARK_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LEVEL_FLD	R/W	0h	Watermark Value. This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark, an interrupt is also generated. This field can be disabled by writing a value of all zeroes.

3.2.6.30 OSPI_INDIRECT_READ_XFER_START_REG Register (Offset = 68h) [reset = 0h]

OSPI_INDIRECT_READ_XFER_START_REG is shown in Figure 12-2004 and described in Table 12-3979.

Return to Summary Table.

Indirect Read Transfer Start Address Register.

This register allows to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.

Table 12-3978 OSPI_INDIRECT_READ_XFER_START_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0068h

Figure 12-2004 OSPI_INDIRECT_READ_XFER_START_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3979 OSPI_INDIRECT_READ_XFER_START_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_FLD	R/W	0h	Start of Indirect Access. This is the start address from which the indirect access will commence its READ operation.

3.2.6.31 OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG Register (Offset = 6Ch) [reset = 0h]

OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG is shown in Figure 12-2005 and described in Table 12-3981.

Return to Summary Table.

Indirect Read Transfer Number Bytes Register.

This register allows to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.

Table 12-3980 OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 006Ch

Figure 12-2005 OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VALUE_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3981 OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VALUE_FLD	R/W	0h	Indirect Number of Bytes. This is the number of bytes that the indirect access will consume This can be bigger than the configured size of SRAM.

3.2.6.32 OSPI_INDIRECT_WRITE_XFER_CTRL_REG Register (Offset = 70h) [reset = 0h]

OSPI_INDIRECT_WRITE_XFER_CTRL_REG is shown in Figure 12-2006 and described in Table 12-3983.

Return to Summary Table.

Indirect Write Transfer Control Register.

This register allows control of the Indirect Write Transfer logic.

Table 12-3982 OSPI_INDIRECT_WRITE_XFER_CTRL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0070h

Figure 12-2006 OSPI_INDIRECT_WRITE_XFER_CTRL_REG Register

31	30	29	28	27	26	25	24
INDIR_WR_XFER_RESV2_FLD
R-0h

23	22	21	20	19	18	17	16
INDIR_WR_XFER_RESV2_FLD
R-0h

15	14	13	12	11	10	9	8
INDIR_WR_XFER_RESV2_FLD
R-0h

7	6	5	4	3	2	1	0
NUM_IND_OPS_DONE_FLD		IND_OPS_DONE_STATUS_FLD	WR_QUEUED_FLD	INDIR_WR_XFER_RESV1_FLD	WR_STATUS_FLD	CANCEL_FLD	START_FLD
R-0h		R/W1C-0h	R-0h	R-0h	R-0h	W-0h	W-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; W = Write Only; -n = value after reset

Table 12-3983 OSPI_INDIRECT_WRITE_XFER_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	INDIR_WR_XFER_RESV2_FLD	R	0h	Reserved
7-6	NUM_IND_OPS_DONE_FLD	R	0h	This field contains the number of indirect operations which have been completed. This is used in conjunction with the OSPI_INDIRECT_WRITE_XFER_CTRL_REG[5] IND_OPS_DONE_STATUS_FLD. It is incremented by hardware when an indirect operation has completed. Write a 1 to OSPI_INDIRECT_WRITE_XFER_CTRL_REG[5] IND_OPS_DONE_STATUS_FLD of this register to decrement it.
5	IND_OPS_DONE_STATUS_FLD	R/W1C	0h	Indirect Completion Status. This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it
4	WR_QUEUED_FLD	R	0h	Two indirect write operations have been queued.
3	INDIR_WR_XFER_RESV1_FLD	R	0h	Reserved
2	WR_STATUS_FLD	R	0h	Indirect Write Status. Indirect write operation in progress [status].
1	CANCEL_FLD	W	0h	Cancel Indirect Write. Writing a 1 to this bit will cancel all ongoing indirect write operations.
0	START_FLD	W	0h	Start Indirect Write. Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation.

3.2.6.33 OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG Register (Offset = 74h) [reset = FFFFFFFFh]

OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG is shown in Figure 12-2007 and described in Table 12-3985.

Return to Summary Table.

Indirect Write Transfer Watermark Register.

This register allows to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered.

Note:

Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.

Table 12-3984 OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0074h

Figure 12-2007 OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LEVEL_FLD
R/W-FFFFFFFFh

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3985 OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LEVEL_FLD	R/W	FFFFFFFFh	Watermark Value. This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark, an interrupt is also generated. This field can be disabled by writing a value of all ones.

3.2.6.34 OSPI_INDIRECT_WRITE_XFER_START_REG Register (Offset = 78h) [reset = 0h]

OSPI_INDIRECT_WRITE_XFER_START_REG is shown in Figure 12-2008 and described in Table 12-3987.

Return to Summary Table.

Indirect Write Transfer Start Address Register.

This register allows to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is triggered.

Table 12-3986 OSPI_INDIRECT_WRITE_XFER_START_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0078h

Figure 12-2008 OSPI_INDIRECT_WRITE_XFER_START_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3987 OSPI_INDIRECT_WRITE_XFER_START_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_FLD	R/W	0h	Start of Indirect Access. This is the start address from which the indirect access will commence its WRITE operation.

3.2.6.35 OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG Register (Offset = 7Ch) [reset = 0h]

OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG is shown in Figure 12-2009 and described in Table 12-3989.

Return to Summary Table.

Indirect Write Transfer Number Bytes Register.

This register allows to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.

Table 12-3988 OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 007Ch

Figure 12-2009 OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VALUE_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3989 OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VALUE_FLD	R/W	0h	Indirect Number of Bytes. This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM.

3.2.6.36 OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Register (Offset = 80h) [reset = 4h]

OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG is shown in Figure 12-2010 and described in Table 12-3991.

Return to Summary Table.

Indirect Trigger Address Range Register.

This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer, there is no need to detect indirect trigger address boundaries by software. This register should be setup before an indirect read transfer is triggered.

Table 12-3990 OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0080h

Figure 12-2010 OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Register

31	30	29	28	27	26	25	24
IND_RANGE_RESV1_FLD
R-0h

23	22	21	20	19	18	17	16
IND_RANGE_RESV1_FLD
R-0h

15	14	13	12	11	10	9	8
IND_RANGE_RESV1_FLD
R-0h

7	6	5	4	3	2	1	0
IND_RANGE_RESV1_FLD				IND_RANGE_WIDTH_FLD
R-0h				R/W-4h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3991 OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IND_RANGE_RESV1_FLD	R	0h	Reserved
3-0	IND_RANGE_WIDTH_FLD	R/W	4h	Indirect Range Width. This is the address offset of the OSPI_IND_AHB_ADDR_TRIGGER_REG. When any valid Indirect Access is triggered and data address fits to the range, the request is forwarded into Indirect Write Controller or Indirect Read Controller depending on which one was requested by valid trigger. The value is given as power of 2. The default one is 2**4 = 16 what allows 16-byte bursts to be performed. This field reflects width of the range so number of locations of valid addresses (single location has 32 bits) ranges from Indirect Trigger Address to Indirect Trigger Address + [Indirect Range Width - 1].

3.2.6.37 OSPI_FLASH_COMMAND_CTRL_MEM_REG Register (Offset = 8Ch) [reset = 0h]

OSPI_FLASH_COMMAND_CTRL_MEM_REG is shown in Figure 12-2011 and described in Table 12-3993.

Return to Summary Table.

Flash Command Control Memory Register.

This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank.

Table 12-3992 OSPI_FLASH_COMMAND_CTRL_MEM_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 008Ch

Figure 12-2011 OSPI_FLASH_COMMAND_CTRL_MEM_REG Register

31	30	29	28	27	26	25	24
FLASH_COMMAND_CTRL_MEM_RESV1_FLD			MEM_BANK_ADDR_FLD
R-0h			R/W-0h

23	22	21	20	19	18	17	16
MEM_BANK_ADDR_FLD				FLASH_COMMAND_CTRL_MEM_RESV2_FLD	NB_OF_STIG_READ_BYTES_FLD
R/W-0h				R-0h	R/W-0h

15	14	13	12	11	10	9	8
MEM_BANK_READ_DATA_FLD
R-0h

7	6	5	4	3	2	1	0
FLASH_COMMAND_CTRL_MEM_RESV3_FLD						MEM_BANK_REQ_IN_PROGRESS_FLD	TRIGGER_MEM_BANK_REQ_FLD
R-0h						R-0h	W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 12-3993 OSPI_FLASH_COMMAND_CTRL_MEM_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	FLASH_COMMAND_CTRL_MEM_RESV1_FLD	R	0h	Reserved
28-20	MEM_BANK_ADDR_FLD	R/W	0h	Memory Bank Address. The address of the Memory Bank which data will be read from. It is equivalent to the index value of the byte read by the last STIG access configured to work with STIG Memory Bank
19	FLASH_COMMAND_CTRL_MEM_RESV2_FLD	R	0h	Reserved
18-16	NB_OF_STIG_READ_BYTES_FLD	R/W	0h	Number of STIG Memory Bank Read Bytes. It defines the number of read bytes for the STIG configured to work with STIG Memory Bank as follows: 0h = 16 bytes 1h = 32 bytes 2h = 64 bytes 3h = 128 bytes 4h = 256 bytes 5h = 512 bytes others = unused
15-8	MEM_BANK_READ_DATA_FLD	R	0h	Memory Bank Read Data. Last requested data from the STIG Memory Bank.
7-2	FLASH_COMMAND_CTRL_MEM_RESV3_FLD	R	0h	Reserved
1	MEM_BANK_REQ_IN_PROGRESS_FLD	R	0h	Memory Bank data request in progress.
0	TRIGGER_MEM_BANK_REQ_FLD	W	0h	Trigger the Memory Bank data request.

3.2.6.38 OSPI_FLASH_CMD_CTRL_REG Register (Offset = 90h) [reset = 0h]

OSPI_FLASH_CMD_CTRL_REG is shown in Figure 12-2012 and described in Table 12-3995.

Return to Summary Table.

Flash Command Control Register.

This register controls SPI transactions generated by STIG. It allows to define corresponding SPI frame to particular command, triggering the transfer and polling for its completion.

Table 12-3994 OSPI_FLASH_CMD_CTRL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0090h

Figure 12-2012 OSPI_FLASH_CMD_CTRL_REG Register

31	30	29	28	27	26	25	24
CMD_OPCODE_FLD
R/W-0h

23	22	21	20	19	18	17	16
ENB_READ_DATA_FLD	NUM_RD_DATA_BYTES_FLD			ENB_COMD_ADDR_FLD	ENB_MODE_BIT_FLD	NUM_ADDR_BYTES_FLD
R/W-0h	R/W-0h			R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
ENB_WRITE_DATA_FLD	NUM_WR_DATA_BYTES_FLD			NUM_DUMMY_CYCLES_FLD
R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
NUM_DUMMY_CYCLES_FLD	FLASH_CMD_CTRL_RESV1_FLD				STIG_MEM_BANK_EN_FLD	CMD_EXEC_STATUS_FLD	CMD_EXEC_FLD
R/W-0h	R-0h				R/W-0h	R-0h	W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 12-3995 OSPI_FLASH_CMD_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	CMD_OPCODE_FLD	R/W	0h	Command Opcode. The command opcode field should be setup before triggering the command. For example, 20h maps to SubSector Erase. Writing to the execute OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD register launches the command. NOTE: Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 0h, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 1h, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2h, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
23	ENB_READ_DATA_FLD	R/W	0h	Read Data Enable. Set to 1 if the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires read data bytes to be received from the device.
22-20	NUM_RD_DATA_BYTES_FLD	R/W	0h	Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes
19	ENB_COMD_ADDR_FLD	R/W	0h	Command Address Enable. Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field.
18	ENB_MODE_BIT_FLD	R/W	0h	Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes
17-16	NUM_ADDR_BYTES_FLD	R/W	0h	Number of Address Bytes. Set to the number of address bytes required [the address itself is programmed in the OSPI_FLASH_CMD_ADDR_REG. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD: 0h = 1 address byte 1h = 2 address bytes 2h = 3 address bytes 3h = 4 address bytes
15	ENB_WRITE_DATA_FLD	R/W	0h	Write Data Enable. Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device.
14-12	NUM_WR_DATA_BYTES_FLD	R/W	0h	Number of Write Data Bytes. Up to 8 Data bytes may be written using this command. Set to 0 for 1 byte, 7 for 8 bytes.
11-7	NUM_DUMMY_CYCLES_FLD	R/W	0h	Number of Dummy cycles. Set to the number of dummy cycles required. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD.
6-3	FLASH_CMD_CTRL_RESV1_FLD	R	0h	Reserved
2	STIG_MEM_BANK_EN_FLD	R/W	0h	STIG Memory Bank enable bit. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD.
1	CMD_EXEC_STATUS_FLD	R	0h	Command execution in progress.
0	CMD_EXEC_FLD	W	0h	Execute the command.

3.2.6.39 OSPI_FLASH_CMD_ADDR_REG Register (Offset = 94h) [reset = 0h]

OSPI_FLASH_CMD_ADDR_REG is shown in Figure 12-2013 and described in Table 12-3997.

Return to Summary Table.

Flash Command Address Register.

This register allows to define the address of the command using by the STIG controller. This register should be setup while the controller is idle.

Table 12-3996 OSPI_FLASH_CMD_ADDR_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 0094h

Figure 12-2013 OSPI_FLASH_CMD_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3997 OSPI_FLASH_CMD_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_FLD	R/W	0h	Command Address. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register It is the address used by the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD bit field.

3.2.6.40 OSPI_FLASH_RD_DATA_LOWER_REG Register (Offset = A0h) [reset = 0h]

OSPI_FLASH_RD_DATA_LOWER_REG is shown in Figure 12-2014 and described in Table 12-3999.

Return to Summary Table.

Flash Command Read Data Register (Lower).

This register keeps the last 4 bytes read by STIG SPI access.

Table 12-3998 OSPI_FLASH_RD_DATA_LOWER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00A0h

Figure 12-2014 OSPI_FLASH_RD_DATA_LOWER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA_FLD
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3999 OSPI_FLASH_RD_DATA_LOWER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA_FLD	R	0h	Command Read Data (Lower). This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.

3.2.6.41 OSPI_FLASH_RD_DATA_UPPER_REG Register (Offset = A4h) [reset = 0h]

OSPI_FLASH_RD_DATA_UPPER_REG is shown in Figure 12-2015 and described in Table 12-4001.

Return to Summary Table.

Flash Command Read Data Register (Upper).

This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the OSPI_FLASH_RD_DATA_LOWER_REG register enables the controller to keep 8 last bytes read from the Flash Device using STIG.

Table 12-4000 OSPI_FLASH_RD_DATA_UPPER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00A4h

Figure 12-2015 OSPI_FLASH_RD_DATA_UPPER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA_FLD
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4001 OSPI_FLASH_RD_DATA_UPPER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA_FLD	R	0h	Command Read Data (Upper). This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.

3.2.6.42 OSPI_FLASH_WR_DATA_LOWER_REG Register (Offset = A8h) [reset = 0h]

OSPI_FLASH_WR_DATA_LOWER_REG is shown in Figure 12-2016 and described in Table 12-4003.

Return to Summary Table.

Flash Command Write Data Register (Lower).

This register takes the first 4 bytes to be written by STIG.

Table 12-4002 OSPI_FLASH_WR_DATA_LOWER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00A8h

Figure 12-2016 OSPI_FLASH_WR_DATA_LOWER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4003 OSPI_FLASH_WR_DATA_LOWER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA_FLD	R/W	0h	Command Write Data Lower Byte. This is the command write data lower byte. This should be setup before triggering the command with the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD bit. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the OSPI_FLASH_CMD_CTRL_REG register.

3.2.6.43 OSPI_FLASH_WR_DATA_UPPER_REG Register (Offset = ACh) [reset = 0h]

OSPI_FLASH_WR_DATA_UPPER_REG is shown in Figure 12-2017 and described in Table 12-4005.

Return to Summary Table.

Flash Command Write Data Register (Upper).

This register takes the bytes ranging from 5 to 8 to be written by STIG.

Table 12-4004 OSPI_FLASH_WR_DATA_UPPER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00ACh

Figure 12-2017 OSPI_FLASH_WR_DATA_UPPER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA_FLD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4005 OSPI_FLASH_WR_DATA_UPPER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA_FLD	R/W	0h	Command Write Data Upper Byte. This is the command write data upper byte. This should be setup before triggering the command with the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD bitr It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the OSPI_FLASH_CMD_CTRL_REG register.

3.2.6.44 OSPI_POLLING_FLASH_STATUS_REG Register (Offset = B0h) [reset = 0h]

OSPI_POLLING_FLASH_STATUS_REG is shown in Figure 12-2018 and described in Table 12-4007.

Return to Summary Table.

Polling Flash Status Register.

This register provides auto-polling data. It acts as the extension for the OSPI_WRITE_COMPLETION_CTRL_REG register where full status is not available and any action can be taken only relying on the indication of single bit being polled for.

Table 12-4006 OSPI_POLLING_FLASH_STATUS_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00B0h

Figure 12-2018 OSPI_POLLING_FLASH_STATUS_REG Register

31	30	29	28	27	26	25	24
DEVICE_STATUS_RSVD_FLD2
R-0h

23	22	21	20	19	18	17	16
DEVICE_STATUS_RSVD_FLD2				DEVICE_STATUS_NB_DUMMY
R-0h				R/W-0h

15	14	13	12	11	10	9	8
DEVICE_STATUS_RSVD_FLD1							DEVICE_STATUS_VALID_FLD
R-0h							R-0h

7	6	5	4	3	2	1	0
DEVICE_STATUS_FLD
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-4007 OSPI_POLLING_FLASH_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	DEVICE_STATUS_RSVD_FLD2	R	0h	Reserved
19-16	DEVICE_STATUS_NB_DUMMY	R/W	0h	Number of dummy cycles for auto-polling.
15-9	DEVICE_STATUS_RSVD_FLD1	R	0h	Reserved
8	DEVICE_STATUS_VALID_FLD	R	0h	Device Status Valid. This should be set when value in bits from 7 to 0 is valid.
7-0	DEVICE_STATUS_FLD	R	0h	Defines actual Status Register of Device.

3.2.6.45 OSPI_PHY_CONFIGURATION_REG Register (Offset = B4h) [reset = 40000000h]

OSPI_PHY_CONFIGURATION_REG is shown in Figure 12-2019 and described in Table 12-4009.

Return to Summary Table.

PHY Configuration Register.

This register defines the configuration of PHY Module and controls the internal DLL. This register should be setup while the controller is idle.

Table 12-4008 OSPI_PHY_CONFIGURATION_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00B4h

Figure 12-2019 OSPI_PHY_CONFIGURATION_REG Register

31	30	29	28	27	26	25	24
PHY_CONFIG_RESYNC_FLD	PHY_CONFIG_RESET_FLD	PHY_CONFIG_RX_DLL_BYPASS_FLD	PHY_CONFIG_RESV2_FLD
W-0h	W-1h	R/W-0h	R-0h

23	22	21	20	19	18	17	16
PHY_CONFIG_RESV2_FLD	PHY_CONFIG_TX_DLL_DELAY_FLD
R-0h	R/W-0h

15	14	13	12	11	10	9	8
PHY_CONFIG_RESV1_FLD
R-0h

7	6	5	4	3	2	1	0
PHY_CONFIG_RESV1_FLD	PHY_CONFIG_RX_DLL_DELAY_FLD
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 12-4009 OSPI_PHY_CONFIGURATION_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PHY_CONFIG_RESYNC_FLD	W	0h	Re-synchronisation DLL. This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields.
30	PHY_CONFIG_RESET_FLD	W	1h	DLL Reset. This bit is used for reset of Delay Lines by software.
29	PHY_CONFIG_RX_DLL_BYPASS_FLD	R/W	0h	RX DLL Bypass. This field determines if RX DLL is bypassed.
28-23	PHY_CONFIG_RESV2_FLD	R	0h	Reserved
22-16	PHY_CONFIG_TX_DLL_DELAY_FLD	R/W	0h	TX DLL Delay. This field determines the number of delay elements to insert on data path between RCLK and SCLK.
15-7	PHY_CONFIG_RESV1_FLD	R	0h	Reserved
6-0	PHY_CONFIG_RX_DLL_DELAY_FLD	R/W	0h	RX DLL Delay. This field determines the number of delay elements to insert on data path between RCLK and sampling clock.

3.2.6.46 OSPI_PHY_MASTER_CONTROL_REG Register (Offset = B8h) [reset = 00800000h]

OSPI_PHY_MASTER_CONTROL_REG is shown in Figure 12-2020 and described in Table 12-4011.

Return to Summary Table.

PHY DLL Master Control Register.

This register defines the configuration and control logic of DLL intended to work in DLL Master Mode.

Table 12-4010 OSPI_PHY_MASTER_CONTROL_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00B8h

Figure 12-2020 OSPI_PHY_MASTER_CONTROL_REG Register

31	30	29	28	27	26	25	24
PHY_MASTER_CONTROL_RESV3_FLD							PHY_MASTER_LOCK_MODE_FLD
R-0h							R/W-0h

23	22	21	20	19	18	17	16
PHY_MASTER_BYPASS_MODE_FLD	PHY_MASTER_PHASE_DETECT_SELECTOR_FLD			PHY_MASTER_CONTROL_RESV2_FLD	PHY_MASTER_NB_INDICATIONS_FLD
R/W-1h	R/W-0h			R-0h	R/W-0h

15	14	13	12	11	10	9	8
PHY_MASTER_CONTROL_RESV1_FLD
R-0h

7	6	5	4	3	2	1	0
PHY_MASTER_CONTROL_RESV1_FLD	PHY_MASTER_INITIAL_DELAY_FLD
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-4011 OSPI_PHY_MASTER_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	PHY_MASTER_CONTROL_RESV3_FLD	R	0h	Reserved
24	PHY_MASTER_LOCK_MODE_FLD	R/W	0h	Determines if the master delay line locks on a full cycle or half cycle of delay. This bit need not be written by software. If DLL does not lock in full cycle, it will automatically try to lock in half cycle mode. 0h = Full cycle of delay 1h = Half cycle of delay
23	PHY_MASTER_BYPASS_MODE_FLD	R/W	1h	Controls the bypass mode of the master and slave DLLs. Controls the bypass mode of the master and slave DLLs. If this bit is set, the bypass mode is intended to be used only for debug. 0h = Master operational mode DLL works in normal mode of operation where the slave delay line settings are used as fractional delay of the master delay line encoder reading of the number of delays in one cycle. 1h = Bypass mode Master DLL is disabled with only 1 delay element in its delay line. The slave delay lines decode delays in absolute delay elements rather than as fractional delays. Delays are defined in OSPI_PHY_CONFIGURATION_REG[22-16] PHY_CONFIG_TX_DLL_DELAY_FLD and OSPI_PHY_CONFIGURATION_REG[6-0] PHY_CONFIG_RX_DLL_ DELAY_FLD bit fields.
22-20	PHY_MASTER_PHASE_DETECT_SELECTOR_FLD	R/W	0h	Selects the number of delay elements to be inserted between the phase detect flip-flops. 0h = One delay element 1h = Two delay element 2h = Three delay element 3h = Four delay element 4h = Five delay element 5h = Six delay element 6h = Seven delay element 7h = Eight delay element
19	PHY_MASTER_CONTROL_RESV2_FLD	R	0h	Reserved
18-16	PHY_MASTER_NB_INDICATIONS_FLD	R/W	0h	Holds the number of consecutive increment or decrement indications.
15-7	PHY_MASTER_CONTROL_RESV1_FLD	R	0h	Reserved
6-0	PHY_MASTER_INITIAL_DELAY_FLD	R/W	0h	This value is the initial delay value for the Master DLL.

3.2.6.47 OSPI_DLL_OBSERVABLE_LOWER_REG Register (Offset = BCh) [reset = 0h]

OSPI_DLL_OBSERVABLE_LOWER_REG is shown in Figure 12-2021 and described in Table 12-4013.

Return to Summary Table.

DLL Observable Register Lower.

This register allows to observe and debug DLL status.

Table 12-4012 OSPI_DLL_OBSERVABLE_LOWER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00BCh

Figure 12-2021 OSPI_DLL_OBSERVABLE_LOWER_REG Register

31	30	29	28	27	26	25	24
DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD
R-0h

23	22	21	20	19	18	17	16
DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD
R-0h

15	14	13	12	11	10	9	8
DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD	DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD
R-0h	R-0h

7	6	5	4	3	2	1	0
DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD					DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD		DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD
R-0h					R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4013 OSPI_DLL_OBSERVABLE_LOWER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD	R	0h	Holds the state of the cumulative lock incremental steps when the OSPI_DLL_OBSERVABLE_LOWER_REG[7-3] DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD of this parameter was triggered to increment or was last saturated at a value of 1Fh.
23-16	DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD	R	0h	Holds the state of the cumulative lock decremental steps when the OSPI_DLL_OBSERVABLE_LOWER_REG[7-3] DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD of this parameter was triggered to decrement or was last saturated at a value of 1Fh.
15	DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD	R	0h	This bit indicates that lock of loopback is done.
14-8	DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD	R	0h	DLL Lock Value. Reports the DLL encoder value from the master DLL to the slave DLLs.
7-3	DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD	R	0h	DLL Unlock Counter. Reports the number of increments or decrements required for the master DLL to complete the locking process.
2-1	DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD	R	0h	DLL Locked Mode. Defines the mode in which the DLL has achieved the lock: 0h = Full clock mode. The master delay line was long enough to lock on one full clock cycle of delay. 1h = Reserved. 2h = Half clock mode. The master delay line was not long enough to lock one full cycle of delay but could lock on a half- cycle of delay. 3h = Saturation mode. The master delay line was not long enough to lock on a full or a half clock cycle. In this mode, the encoder value is fixed at the maximum delay line setting and the master DLL will be disabled. The slave delay lines continue to use the fractional delays based upon the fixed saturation value of the delay line.
0	DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD	R	0h	DLL Lock. Indicates status of DLL 0h = DLL has not locked 1h = DLL is locked

3.2.6.48 OSPI_DLL_OBSERVABLE_UPPER_REG Register (Offset = C0h) [reset = 0h]

OSPI_DLL_OBSERVABLE_UPPER_REG is shown in Figure 12-2022 and described in Table 12-4015.

Return to Summary Table.

DLL Observable Register Upper.

This register allows to observe and debug DLL status.

Table 12-4014 OSPI_DLL_OBSERVABLE_UPPER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00C0h

Figure 12-2022 OSPI_DLL_OBSERVABLE_UPPER_REG Register

31	30	29	28	27	26	25	24
DLL_OBSERVABLE_UPPER_RESV2_FLD
R-0h

23	22	21	20	19	18	17	16
DLL_OBSERVABLE_UPPER_RESV2_FLD	DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD
R-0h	R-0h

15	14	13	12	11	10	9	8
DLL_OBSERVABLE_UPPER_RESV1_FLD
R-0h

7	6	5	4	3	2	1	0
DLL_OBSERVABLE_UPPER_RESV1_FLD	DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4015 OSPI_DLL_OBSERVABLE_UPPER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	DLL_OBSERVABLE_UPPER_RESV2_FLD	R	0h	Reserved
22-16	DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD	R	0h	TX DLL decoder output. Holds the encoded value for the TX delay line for this slice.
15-7	DLL_OBSERVABLE_UPPER_RESV1_FLD	R	0h	Reserved
6-0	DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD	R	0h	RX DLL decoder output. Holds the encoded value for the RX delay line for this slice.

3.2.6.49 OSPI_OPCODE_EXT_LOWER_REG Register (Offset = E0h) [reset = 13EDFA00h]

OSPI_OPCODE_EXT_LOWER_REG is shown in Figure 12-2023 and described in Table 12-4017.

Return to Summary Table.

Opcode Extension Register (Lower).

This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by OSPI_CONFIG_REG[30] DUAL_BYTE_OPCODE_EN_FLD bit.

Table 12-4016 OSPI_OPCODE_EXT_LOWER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00E0h

Figure 12-2023 OSPI_OPCODE_EXT_LOWER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXT_READ_OPCODE_FLD								EXT_WRITE_OPCODE_FLD
R/W-13h								R/W-EDh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXT_POLL_OPCODE_FLD								EXT_STIG_OPCODE_FLD
R/W-FAh								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4017 OSPI_OPCODE_EXT_LOWER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	EXT_READ_OPCODE_FLD	R/W	13h	Supplement byte of any Read Opcoded defined in the OSPI_DEV_INSTR_RD_CONFIG_REG[7-0] RD_OPCODE_NON_XIP_FLD bit field.
23-16	EXT_WRITE_OPCODE_FLD	R/W	EDh	Supplement byte of any Write Opcode defined in the OSPI_DEV_INSTR_WR_CONFIG_REG[7-0] WR_OPCODE_FLD bit field.
15-8	EXT_POLL_OPCODE_FLD	R/W	FAh	Supplement byte of any Polling Opcode defined in the OSPI_WRITE_COMPLETION_CTRL_REG[7-0] OPCODE_FLD bit field.
7-0	EXT_STIG_OPCODE_FLD	R/W	0h	Supplement byte of any STIG Opcode defined in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD bit field.

3.2.6.50 OSPI_OPCODE_EXT_UPPER_REG Register (Offset = E4h) [reset = 06F90000h]

OSPI_OPCODE_EXT_UPPER_REG is shown in Figure 12-2024 and described in Table 12-4019.

Return to Summary Table.

Opcode Extension Register (Upper).

This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by OSPI_CONFIG_REG[30] DUAL_BYTE_OPCODE_EN_FLD bit.

Table 12-4018 OSPI_OPCODE_EXT_UPPER_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00E4h

Figure 12-2024 OSPI_OPCODE_EXT_UPPER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WEL_OPCODE_FLD								EXT_WEL_OPCODE_FLD
R/W-6h								R/W-F9h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPCODE_EXT_UPPER_RESV1_FLD
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-4019 OSPI_OPCODE_EXT_UPPER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	WEL_OPCODE_FLD	R/W	6h	WEL Opcode byte 1. First byte of any WEL Opcode
23-16	EXT_WEL_OPCODE_FLD	R/W	F9h	WEL Opcode byte 2 (Optional). Supplement byte of any WEL Opcode
15-0	OPCODE_EXT_UPPER_RESV1_FLD	R	0h	Reserved

3.2.6.51 OSPI_MODULE_ID_REG Register (Offset = FCh) [reset = 03000300h]

OSPI_MODULE_ID_REG is shown in Figure 12-2025 and described in Table 12-4021.

Return to Summary Table.

Module ID Register.

This register provides the IP release number and the configuration data.

Table 12-4020 OSPI_MODULE_ID_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_CTRL	4704 00FCh

Figure 12-2025 OSPI_MODULE_ID_REG Register

31	30	29	28	27	26	25	24
FIX_PATCH_FLD
R-3h

23	22	21	20	19	18	17	16
MODULE_ID_FLD
R-3h

15	14	13	12	11	10	9	8
MODULE_ID_FLD
R-3h

7	6	5	4	3	2	1	0
MODULE_ID_RESV_FLD						CONF_FLD
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4021 OSPI_MODULE_ID_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	FIX_PATCH_FLD	R	3h	Fix/path number related to revision described by 3 LSBs of this register
23-8	MODULE_ID_FLD	R	3h	Module/Revision ID number
7-2	MODULE_ID_RESV_FLD	R	0h	Reserved
1-0	CONF_FLD	R	0h	Configuration ID number: 0h = OCTAL + PHY Configuration 1h = OCTAL Configuration 2h = QUAD + PHY Configuration 3h = QUAD Configuration

3.2.6.52 OSPI_ECC_AGGR Registers

Table 12-4023 lists the memory-mapped registers for the OSPI ECC Aggregator. All register offset addresses not listed in Table 12-4023 should be considered as reserved locations and the register contents should not be modified.

Table 12-4022 OSPI_ECC_AGGR Instances

Instance	Base Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8000h

Table 12-4023 OSPI_ECC_AGGR Registers

Offset	Acronym	Register Name	MCU_FSS0_OSPI0_ECC_AGGR Physical Address
0h	OSPI_ECC_REV	Aggregator revision register	4706 8000h
8h	OSPI_ECC_VECTOR	ECC vector register	4706 8008h
Ch	OSPI_ECC_STAT	Miscellaneous status register	4706 800Ch
10h + formula	OSPI_RESERVED_SVBUS_Y	Reserved area for serial VBUS registers	4706 8010h + formula
3Ch	OSPI_ECC_SEC_EOI_REG	SEC end of interrupt register	4706 803Ch
40h	OSPI_ECC_SEC_STATUS_REG0	SEC interrupt status register 0	4706 8040h
80h	OSPI_ECC_SEC_ENABLE_SET_REG0	SEC interrupt enable set register 0	4706 8080h
C0h	OSPI_ECC_SEC_ENABLE_CLR_REG0	SEC interrupt enable clear register 0	4706 80C0h
13Ch	OSPI_ECC_DED_EOI_REG	DED end of interrupt register	4706 813Ch
140h	OSPI_ECC_DED_STATUS_REG0	DED interrupt status register 0	4706 8140h
180h	OSPI_ECC_DED_ENABLE_SET_REG0	DED interrupt enable set register 0	4706 8180h
1C0h	OSPI_ECC_DED_ENABLE_CLR_REG0	DED interrupt enable clear register 0	4706 81C0h
200h	OSPI_ECC_AGGR_ENABLE_SET	Aggregator interrupt enable set register	4706 8200h
204h	OSPI_ECC_AGGR_ENABLE_CLR	Aggregator interrupt enable clear register	4706 8204h
208h	OSPI_ECC_AGGR_STATUS_SET	Aggregator interrupt status set register	4706 8208h
20Ch	OSPI_ECC_AGGR_STATUS_CLR	Aggregator interrupt status clear register	4706 820Ch

3.2.6.53 OSPI_ECC_REV Register (Offset = 0h) [reset = 66A0EA00h]

OSPI_ECC_REV is shown in Figure 12-2026 and described in Table 12-4025.

Return to Summary Table.

Revision parameters.

Table 12-4024 OSPI_ECC_REV Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8000h

Figure 12-2026 OSPI_ECC_REV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE_ID
R-1h		R-2h		R-6A0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REVRTL					REVMAJ			CUSTOM		REVMIN
R-1Dh					R-2h			R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-4025 OSPI_ECC_REV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Scheme
29-28	BU	R	2h	bu
27-16	MODULE_ID	R	6A0h	Module ID
15-11	REVRTL	R	1Dh	RTL version
10-8	REVMAJ	R	2h	Major version
7-6	CUSTOM	R	0h	Custom version
5-0	REVMIN	R	0h	Minor version

3.2.6.54 OSPI_ECC_VECTOR Register (Offset = 8h) [reset = 0h]

OSPI_ECC_VECTOR is shown in Figure 12-2027 and described in Table 12-4027.

Return to Summary Table.

ECC Vector Register.

Table 12-4026 OSPI_ECC_VECTOR Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8008h

Figure 12-2027 OSPI_ECC_VECTOR Register

31	30	29	28	27	26	25	24
RESERVED							RD_SVBUS_DONE
R-0h							R/W1C-0h

23	22	21	20	19	18	17	16
RD_SVBUS_ADDRESS
R/W-0h

15	14	13	12	11	10	9	8
RD_SVBUS	RESERVED				ECC_VECTOR
R/W1S-0h	R-0h				R/W-0h

7	6	5	4	3	2	1	0
ECC_VECTOR
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4027 OSPI_ECC_VECTOR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RD_SVBUS_DONE	R/W1C	0h	Status to indicate if read on serial VBUS is complete, write of any value will clear this bit.
23-16	RD_SVBUS_ADDRESS	R/W	0h	Read address
15	RD_SVBUS	R/W1S	0h	Write 1 to trigger a read on the serial VBUS
14-11	RESERVED	R	0h	Reserved
10-0	ECC_VECTOR	R/W	0h	Value written to select the corresponding ECC RAM for control or status

3.2.6.55 OSPI_ECC_STAT Register (Offset = Ch) [reset = 1h]

OSPI_ECC_STAT is shown in Figure 12-2028 and described in Table 12-4029.

Return to Summary Table.

Miscellaneous status register.

Table 12-4028 OSPI_ECC_STAT Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 800Ch

Figure 12-2028 OSPI_ECC_STAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																					NUM_RAMS
R-0h																					R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-4029 OSPI_ECC_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-0	NUM_RAMS	R	1h	Indicates the number of RAMs serviced by the ECC aggregator.

3.2.6.56 OSPI_RESERVED_SVBUS_Y Register (Offset = 10h+formula) [reset = 0h]

OSPI_RESERVED_SVBUS_Y is shown in Figure 12-2029 and described in .

Return to Summary Table.

Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.

Offset = 10h + (y * 4h); where y = 0h to 7h

Table 12-4030 OSPI_RESERVED_SVBUS_Y Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8010h + formula

Figure 12-2029 OSPI_RESERVED_SVBUS_Y Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-4031 OSPI_RESERVED_SVBUS_Y Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA	R/W	0h	Serial VBUS register data

3.2.6.57 OSPI_ECC_SEC_EOI_REG Register (Offset = 3Ch) [reset = 0h]

OSPI_ECC_SEC_EOI_REG is shown in Figure 12-2030 and described in Table 12-4033.

Return to Summary Table.

EOI Register

Table 12-4032 OSPI_ECC_SEC_EOI_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 803Ch

Figure 12-2030 OSPI_ECC_SEC_EOI_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EOI_WR
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4033 OSPI_ECC_SEC_EOI_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EOI_WR	R/W1S	0h	EOI Register

3.2.6.58 OSPI_ECC_SEC_STATUS_REG0 Register (Offset = 40h) [reset = 0h]

OSPI_ECC_SEC_STATUS_REG0 is shown in Figure 12-2031 and described in Table 12-4035.

Return to Summary Table.

Interrupt Status Register 0.

Table 12-4034 OSPI_ECC_SEC_STATUS_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8040h

Figure 12-2031 OSPI_ECC_SEC_STATUS_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_PEND
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4035 OSPI_ECC_SEC_STATUS_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_PEND	R/W1S	0h	Interrupt Pending Status for sram_pend

3.2.6.59 OSPI_ECC_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = 0h]

OSPI_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2032 and described in Table 12-4037.

Return to Summary Table.

Interrupt Enable Set Register 0.

Table 12-4036 OSPI_ECC_SEC_ENABLE_SET_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8080h

Figure 12-2032 OSPI_ECC_SEC_ENABLE_SET_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_ENABLE_SET
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4037 OSPI_ECC_SEC_ENABLE_SET_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_ENABLE_SET	R/W1S	0h	Interrupt Enable Set Register for sram_pend

3.2.6.60 OSPI_ECC_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = 0h]

OSPI_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2033 and described in Table 12-4039.

Return to Summary Table.

Interrupt Enable Clear Register 0.

Table 12-4038 OSPI_ECC_SEC_ENABLE_CLR_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 80C0h

Figure 12-2033 OSPI_ECC_SEC_ENABLE_CLR_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_ENABLE_CLR
R-0h							R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-4039 OSPI_ECC_SEC_ENABLE_CLR_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_ENABLE_CLR	R/W1C	0h	Interrupt Enable Clear Register for sram_pend

3.2.6.61 OSPI_ECC_DED_EOI_REG Register (Offset = 13Ch) [reset = 0h]

OSPI_ECC_DED_EOI_REG is shown in Figure 12-2034 and described in Table 12-4041.

Return to Summary Table.

EOI Register.

Table 12-4040 OSPI_ECC_DED_EOI_REG Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 813Ch

Figure 12-2034 OSPI_ECC_DED_EOI_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EOI_WR
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4041 OSPI_ECC_DED_EOI_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EOI_WR	R/W1S	0h	EOI Register

3.2.6.62 OSPI_ECC_DED_STATUS_REG0 Register (Offset = 140h) [reset = 0h]

OSPI_ECC_DED_STATUS_REG0 is shown in Figure 12-2035 and described in Table 12-4043.

Return to Summary Table.

Interrupt Status Register 0.

Table 12-4042 OSPI_ECC_DED_STATUS_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8140h

Figure 12-2035 OSPI_ECC_DED_STATUS_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_PEND
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4043 OSPI_ECC_DED_STATUS_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_PEND	R/W1S	0h	Interrupt Pending Status for sram_pend.

3.2.6.63 OSPI_ECC_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = 0h]

OSPI_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2036 and described in Table 12-4045.

Return to Summary Table.

Interrupt Enable Set Register 0.

Table 12-4044 OSPI_ECC_DED_ENABLE_SET_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8180h

Figure 12-2036 OSPI_ECC_DED_ENABLE_SET_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_ENABLE_SET
R-0h							R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4045 OSPI_ECC_DED_ENABLE_SET_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_ENABLE_SET	R/W1S	0h	Interrupt Enable Set Register for sram_pend.

3.2.6.64 OSPI_ECC_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = 0h]

OSPI_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2037 and described in Table 12-4047.

Return to Summary Table.

Interrupt Enable Clear Register 0.

Table 12-4046 OSPI_ECC_DED_ENABLE_CLR_REG0 Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 81C0h

Figure 12-2037 OSPI_ECC_DED_ENABLE_CLR_REG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SRAM_ENABLE_CLR
R-0h							R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-4047 OSPI_ECC_DED_ENABLE_CLR_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SRAM_ENABLE_CLR	R/W1C	0h	Interrupt Enable Clear Register for sram_pend.

3.2.6.65 OSPI_ECC_AGGR_ENABLE_SET Register (Offset = 200h) [reset = 0h]

OSPI_ECC_AGGR_ENABLE_SET is shown in Figure 12-2038 and described in Table 12-4049.

Return to Summary Table.

AGGR interrupt enable set register.

Table 12-4048 OSPI_ECC_AGGR_ENABLE_SET Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8200h

Figure 12-2038 OSPI_ECC_AGGR_ENABLE_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						TIMEOUT	PARITY
R-0h						R/W1S-0h	R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 12-4049 OSPI_ECC_AGGR_ENABLE_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	TIMEOUT	R/W1S	0h	Interrupt enable set for svbus timeout errors.
0	PARITY	R/W1S	0h	Interrupt enable set for parity errors.

3.2.6.66 OSPI_ECC_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = 0h]

OSPI_ECC_AGGR_ENABLE_CLR is shown in Figure 12-2039 and described in Table 12-4051.

Return to Summary Table.

AGGR interrupt enable clear register.

Table 12-4050 OSPI_ECC_AGGR_ENABLE_CLR Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8204h

Figure 12-2039 OSPI_ECC_AGGR_ENABLE_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						TIMEOUT	PARITY
R-0h						R/W1C-0h	R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-4051 OSPI_ECC_AGGR_ENABLE_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	TIMEOUT	R/W1C	0h	Interrupt enable clear for svbus timeout errors.
0	PARITY	R/W1C	0h	Interrupt enable clear for parity errors.

3.2.6.67 OSPI_ECC_AGGR_STATUS_SET Register (Offset = 208h) [reset = 0h]

OSPI_ECC_AGGR_STATUS_SET is shown in Figure 12-2040 and described in Table 12-4053.

Return to Summary Table.

AGGR interrupt status set register.

Table 12-4052 OSPI_ECC_AGGR_STATUS_SET Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 8208h

Figure 12-2040 OSPI_ECC_AGGR_STATUS_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				TIMEOUT		PARITY
R-0h				R/Wincr-0h		R/Wincr-0h

LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset

Table 12-4053 OSPI_ECC_AGGR_STATUS_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-2	TIMEOUT	R/Wincr	0h	Interrupt status set for svbus timeout errors.
1-0	PARITY	R/Wincr	0h	Interrupt status set for parity errors.

3.2.6.68 OSPI_ECC_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = 0h]

OSPI_ECC_AGGR_STATUS_CLR is shown in Figure 12-2041 and described in Table 12-4055.

Return to Summary Table.

AGGR interrupt status clear register.

Table 12-4054 OSPI_ECC_AGGR_STATUS_CLR Instances

Instance	Physical Address
MCU_FSS0_OSPI0_ECC_AGGR	4706 820Ch

Figure 12-2041 OSPI_ECC_AGGR_STATUS_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				TIMEOUT		PARITY
R-0h				R/Wdecr-0h		R/Wdecr-0h

LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset

Table 12-4055 OSPI_ECC_AGGR_STATUS_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-2	TIMEOUT	R/Wdecr	0h	Interrupt status clear for svbus timeout errors.
1-0	PARITY	R/Wdecr	0h	Interrupt status clear for parity errors.