SPRUIU1 User guide

SPRUIU1D July 2020 – December 2024 DRA821U , DRA821U-Q1

5.4.6.2 PLL0_CFG Registers

Table 5-1678 lists the PLL0_CFG registers. All register offset addresses not listed in Table 5-1678 should be considered as reserved locations and the register contents should not be modified.

Table 5-1677 PLL0_CFG Instances

Instance	Base Address
PLL0_CFG	0068 0000h

Table 5-1678 PLL0_CFG Registers

Offset	Acronym	Register Name	PLL0_CFG Physical Address
0h	PLL0_PID	Peripheral Identification Register	0068 0000h
8h	PLL0_CFG	PLL MMR Configuration	0068 0008h
10h	PLL0_LOCKKEY0	PLL0 Lock Key 0 Register	0068 0010h
14h	PLL0_LOCKKEY1	PLL0 Lock Key 1 RegisterAddr	0068 0014h
20h	PLL0_CTRL	PLL0 Control	0068 0020h
24h	PLL0_STAT	PLL0 Status	0068 0024h
30h	PLL0_FREQ_CTRL0	PLL0 Frequency Control 0 Register	0068 0030h
34h	PLL0_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 0034h
38h	PLL0_DIV_CTRL	PLL0 Output Clock Divider Register	0068 0038h
40h	PLL0_SS_CTRL	PLL_SS_CTRL register for PLL0	0068 0040h
44h	PLL0_SS_SPREAD	PLL_SS_SPREAD register for PLL0	0068 0044h
80h	PLL0_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL0	0068 0080h
84h	PLL0_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL0	0068 0084h
88h	PLL0_HSDIV_CTRL2	HSDIV_CTRL2 register for PLL0	0068 0088h
8Ch	PLL0_HSDIV_CTRL3	HSDIV_CTRL3 register for PLL0	0068 008Ch
90h	PLL0_HSDIV_CTRL4	HSDIV_CTRL4 register for PLL0	0068 0090h
94h	PLL0_HSDIV_CTRL5	HSDIV_CTRL5 register for PLL0	0068 0094h
98h	PLL0_HSDIV_CTRL6	HSDIV_CTRL6 register for PLL0	0068 0098h
9Ch	PLL0_HSDIV_CTRL7	HSDIV_CTRL7 register for PLL0	0068 009Ch
1000h	PLL1_PID	Peripheral Identification Register	0068 1000h
1008h	PLL1_CFG	PLL MMR Configuration	0068 1008h
1010h	PLL1_LOCKKEY0	PLL1 Lock Key 0 Register	0068 1010h
1014h	PLL1_LOCKKEY1	PLL1 Lock Key 1 RegisterAddr	0068 1014h
1020h	PLL1_CTRL	PLL1 Control	0068 1020h
1024h	PLL1_STAT	PLL1 Status	0068 1024h
1030h	PLL1_FREQ_CTRL0	PLL1 Frequency Control 1 Register	0068 1030h
1034h	PLL1_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 1034h
1038h	PLL1_DIV_CTRL	PLL1 Output Clock Divider Register	0068 1038h
1040h	PLL1_SS_CTRL	PLL_SS_CTRL register for PLL1	0068 1040h
1044h	PLL1_SS_SPREAD	PLL_SS_SPREAD register for PLL1	0068 1044h
1080h	PLL1_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL1	0068 1080h
1084h	PLL1_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL1	0068 1084h
1088h	PLL1_HSDIV_CTRL2	HSDIV_CTRL2 register for PLL1	0068 1088h
108Ch	PLL1_HSDIV_CTRL3	HSDIV_CTRL3 register for PLL1	0068 108Ch
1090h	PLL1_HSDIV_CTRL4	HSDIV_CTRL4 register for PLL1	0068 1090h
1094h	PLL1_HSDIV_CTRL5	HSDIV_CTRL5 register for PLL1	0068 1094h
109Ch	PLL1_HSDIV_CTRL7	HSDIV_CTRL7 register for PLL1	0068 109Ch
2000h	PLL2_PID	Peripheral Identification Register	0068 2000h
2008h	PLL2_CFG	PLL MMR Configuration	0068 2008h
2010h	PLL2_LOCKKEY0	PLL2 Lock Key 0 Register	0068 2010h
2014h	PLL2_LOCKKEY1	PLL2 Lock Key 1 RegisterAddr	0068 2014h
2020h	PLL2_CTRL	PLL2 Control	0068 2020h
2024h	PLL2_STAT	PLL2 Status	0068 2024h
2030h	PLL2_FREQ_CTRL0	PLL2 Frequency Control 2 Register	0068 2030h
2034h	PLL2_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 2034h
2038h	PLL2_DIV_CTRL	PLL2 Output Clock Divider Register	0068 2038h
2040h	PLL2_SS_CTRL	PLL_SS_CTRL register for PLL2	0068 2040h
2044h	PLL2_SS_SPREAD	PLL_SS_SPREAD register for PLL2	0068 2044h
2080h	PLL2_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL2	0068 2080h
2084h	PLL2_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL2	0068 2084h
2088h	PLL2_HSDIV_CTRL2	HSDIV_CTRL2 register for PLL2	0068 2088h
208Ch	PLL2_HSDIV_CTRL3	HSDIV_CTRL3 register for PLL2	0068 208Ch
2090h	PLL2_HSDIV_CTRL4	HSDIV_CTRL4 register for PLL2	0068 2090h
2098h	PLL2_HSDIV_CTRL6	HSDIV_CTRL6 register for PLL2	0068 2098h
3000h	PLL3_PID	Peripheral Identification Register	0068 3000h
3008h	PLL3_CFG	PLL MMR Configuration	0068 3008h
3010h	PLL3_LOCKKEY0	PLL3 Lock Key 0 Register	0068 3010h
3014h	PLL3_LOCKKEY1	PLL3 Lock Key 1 RegisterAddr	0068 3014h
3020h	PLL3_CTRL	PLL3 Control	0068 3020h
3024h	PLL3_STAT	PLL3 Status	0068 3024h
3030h	PLL3_FREQ_CTRL0	PLL3 Frequency Control 3 Register	0068 3030h
3034h	PLL3_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 3034h
3038h	PLL3_DIV_CTRL	PLL3 Output Clock Divider Register	0068 3038h
3040h	PLL3_SS_CTRL	PLL_SS_CTRL register for PLL3	0068 3040h
3044h	PLL3_SS_SPREAD	PLL_SS_SPREAD register for PLL3	0068 3044h
3080h	PLL3_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL3	0068 3080h
3084h	PLL3_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL3	0068 3084h
3088h	PLL3_HSDIV_CTRL2	HSDIV_CTRL2 register for PLL3	0068 3088h
308Ch	PLL3_HSDIV_CTRL3	HSDIV_CTRL3 register for PLL3	0068 308Ch
3090h	PLL3_HSDIV_CTRL4	HSDIV_CTRL4 register for PLL3	0068 3090h
4000h	PLL4_PID	Peripheral Identification Register	0068 4000h
4008h	PLL4_CFG	PLL MMR Configuration	0068 4008h
4010h	PLL4_LOCKKEY0	PLL4 Lock Key 0 Register	0068 4010h
4014h	PLL4_LOCKKEY1	PLL4 Lock Key 1 RegisterAddr	0068 4014h
4020h	PLL4_CTRL	PLL4 Control	0068 4020h
4024h	PLL4_STAT	PLL4 Status	0068 4024h
4030h	PLL4_FREQ_CTRL0	PLL4 Frequency Control 4 Register	0068 4030h
4034h	PLL4_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 4034h
4038h	PLL4_DIV_CTRL	PLL4 Output Clock Divider Register	0068 4038h
4040h	PLL4_SS_CTRL	PLL_SS_CTRL register for PLL4	0068 4040h
4044h	PLL4_SS_SPREAD	PLL_SS_SPREAD register for PLL4	0068 4044h
4080h	PLL4_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL4	0068 4080h
4084h	PLL4_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL4	0068 4084h
4088h	PLL4_HSDIV_CTRL2	HSDIV_CTRL2 register for PLL4	0068 4088h
7000h	PLL7_PID	Peripheral Identification Register	0068 7000h
7008h	PLL7_CFG	PLL MMR Configuration	0068 7008h
7010h	PLL7_LOCKKEY0	PLL7 Lock Key 0 Register	0068 7010h
7014h	PLL7_LOCKKEY1	PLL7 Lock Key 1 RegisterAddr	0068 7014h
7020h	PLL7_CTRL	PLL7 Control	0068 7020h
7024h	PLL7_STAT	PLL7 Status	0068 7024h
7030h	PLL7_FREQ_CTRL0	PLL7 Frequency Control 7 Register	0068 7030h
7034h	PLL7_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 7034h
7038h	PLL7_DIV_CTRL	PLL7 Output Clock Divider Register	0068 7038h
7040h	PLL7_SS_CTRL	PLL_SS_CTRL register for PLL7	0068 7040h
7044h	PLL7_SS_SPREAD	PLL_SS_SPREAD register for PLL7	0068 7044h
7060h	PLL7_CAL_CTRL	PLL7 Calibration Control Register	0068 7060h
7064h	PLL7_CAL_STAT	PLL7 Calibration Status Register	0068 7064h
7080h	PLL7_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL7	0068 7080h
8000h	PLL8_PID	Peripheral Identification Register	0068 8000h
8008h	PLL8_CFG	PLL MMR Configuration	0068 8008h
8010h	PLL8_LOCKKEY0	PLL8 Lock Key 0 Register	0068 8010h
8014h	PLL8_LOCKKEY1	PLL8 Lock Key 1 RegisterAddr	0068 8014h
8020h	PLL8_CTRL	PLL8 Control	0068 8020h
8024h	PLL8_STAT	PLL8 Status	0068 8024h
8030h	PLL8_FREQ_CTRL0	PLL8 Frequency Control 8 Register	0068 8030h
8034h	PLL8_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 8034h
8038h	PLL8_DIV_CTRL	PLL8 Output Clock Divider Register	0068 8038h
8040h	PLL8_SS_CTRL	PLL_SS_CTRL register for PLL8	0068 8040h
8044h	PLL8_SS_SPREAD	PLL_SS_SPREAD register for PLL8	0068 8044h
8060h	PLL8_CAL_CTRL	PLL8 Calibration Control Register	0068 8060h
8064h	PLL8_CAL_STAT	PLL8 Calibration Status Register	0068 8064h
8080h	PLL8_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL8	0068 8080h
C000h	PLL12_PID	Peripheral Identification Register	0068 C000h
C008h	PLL12_CFG	PLL MMR Configuration	0068 C008h
C010h	PLL12_LOCKKEY0	PLL12 Lock Key 0 Register	0068 C010h
C014h	PLL12_LOCKKEY1	PLL12 Lock Key 1 RegisterAddr	0068 C014h
C020h	PLL12_CTRL	PLL12 Control	0068 C020h
C024h	PLL12_STAT	PLL12 Status	0068 C024h
C030h	PLL12_FREQ_CTRL0	PLL12 Frequency Control 12 Register	0068 C030h
C034h	PLL12_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 C034h
C038h	PLL12_DIV_CTRL	PLL12 Output Clock Divider Register	0068 C038h
C040h	PLL12_SS_CTRL	PLL_SS_CTRL register for PLL12	0068 C040h
C044h	PLL12_SS_SPREAD	PLL_SS_SPREAD register for PLL12	0068 C044h
C060h	PLL12_CAL_CTRL	PLL12 Calibration Control Register	0068 C060h
C064h	PLL12_CAL_STAT	PLL12 Calibration Status Register	0068 C064h
C080h	PLL12_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL12	0068 C080h
E000h	PLL14_PID	Peripheral Identification Register	0068 E000h
E008h	PLL14_CFG	PLL MMR Configuration	0068 E008h
E010h	PLL14_LOCKKEY0	PLL14 Lock Key 0 Register	0068 E010h
E014h	PLL14_LOCKKEY1	PLL14 Lock Key 1 RegisterAddr	0068 E014h
E020h	PLL14_CTRL	PLL14 Control	0068 E020h
E024h	PLL14_STAT	PLL14 Status	0068 E024h
E030h	PLL14_FREQ_CTRL0	PLL14 Frequency Control 14 Register	0068 E030h
E034h	PLL14_FREQ_CTRL1	PLL0 Frequency Control 1 Register	0068 E034h
E038h	PLL14_DIV_CTRL	PLL14 Output Clock Divider Register	0068 E038h
E040h	PLL14_SS_CTRL	PLL_SS_CTRL register for PLL14	0068 E040h
E044h	PLL14_SS_SPREAD	PLL_SS_SPREAD register for PLL14	0068 E044h
E080h	PLL14_HSDIV_CTRL0	HSDIV_CTRL0 register for PLL14	0068 E080h
E084h	PLL14_HSDIV_CTRL1	HSDIV_CTRL1 register for PLL14	0068 E084h

4.6.2.1 PLL0_PID Register (Offset = 0h) [reset = 61801001h]

PLL0_PID is shown in Figure 5-811 and described in Table 5-1680.

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Peripheral Identification Register

Table 5-1679 PLL0_PID Instances

Instance	Physical Address
PLL0_CFG	0068 0000h

Figure 5-811 PLL0_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1680 PLL0_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.2 PLL0_CFG Register (Offset = 8h) [reset = X]

PLL0_CFG is shown in Figure 5-812 and described in Table 5-1682.

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PLL MMR Configuration

Table 5-1681 PLL0_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 0008h

Figure 5-812 PLL0_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-FFh

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-FFh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1682 PLL0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	FFh	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.3 PLL0_LOCKKEY0 Register (Offset = 10h) [reset = 0h]

PLL0_LOCKKEY0 is shown in Figure 5-813 and described in Table 5-1684.

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PLL0 Lock Key 0 Register

Table 5-1683 PLL0_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 0010h

Figure 5-813 PLL0_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1684 PLL0_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.4 PLL0_LOCKKEY1 Register (Offset = 14h) [reset = 0h]

PLL0_LOCKKEY1 is shown in Figure 5-814 and described in Table 5-1686.

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PLL0 Lock Key 1 RegisterAddr

Table 5-1685 PLL0_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 0014h

Figure 5-814 PLL0_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1686 PLL0_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

4.6.2.5 PLL0_CTRL Register (Offset = 20h) [reset = X]

PLL0_CTRL is shown in Figure 5-815 and described in Table 5-1688.

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PLL0 Control

Table 5-1687 PLL0_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0020h

Figure 5-815 PLL0_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1688 PLL0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.6 PLL0_STAT Register (Offset = 24h) [reset = X]

PLL0_STAT is shown in Figure 5-816 and described in Table 5-1690.

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PLL0 Status

Table 5-1689 PLL0_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 0024h

Figure 5-816 PLL0_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1690 PLL0_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.7 PLL0_FREQ_CTRL0 Register (Offset = 30h) [reset = X]

PLL0_FREQ_CTRL0 is shown in Figure 5-817 and described in Table 5-1692.

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PLL0 Frequency Control 0 Register

Table 5-1691 PLL0_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 0030h

Figure 5-817 PLL0_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1692 PLL0_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.8 PLL0_FREQ_CTRL1 Register (Offset = 34h) [reset = X]

PLL0_FREQ_CTRL1 is shown in Figure 5-818 and described in Table 5-1694.

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PLL0 Frequency Control 1 Register

Table 5-1693 PLL0_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 0034h

Figure 5-818 PLL0_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1694 PLL0_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.9 PLL0_DIV_CTRL Register (Offset = 38h) [reset = X]

PLL0_DIV_CTRL is shown in Figure 5-819 and described in Table 5-1696.

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PLL0 Output Clock Divider Register

Table 5-1695 PLL0_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0038h

Figure 5-819 PLL0_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1696 PLL0_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.10 PLL0_SS_CTRL Register (Offset = 40h) [reset = X]

PLL0_SS_CTRL is shown in Figure 5-820 and described in Table 5-1698.

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PLL_SS_CTRL register for PLL0

Table 5-1697 PLL0_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 0040h

Figure 5-820 PLL0_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1698 PLL0_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.11 PLL0_SS_SPREAD Register (Offset = 44h) [reset = X]

PLL0_SS_SPREAD is shown in Figure 5-821 and described in Table 5-1700.

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PLL_SS_SPREAD register for PLL0

Table 5-1699 PLL0_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 0044h

Figure 5-821 PLL0_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1700 PLL0_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.12 PLL0_HSDIV_CTRL0 Register (Offset = 80h) [reset = X]

PLL0_HSDIV_CTRL0 is shown in Figure 5-822 and described in Table 5-1702.

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HSDIV_CTRL0 register for PLL0

Table 5-1701 PLL0_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 0080h

Figure 5-822 PLL0_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1702 PLL0_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.13 PLL0_HSDIV_CTRL1 Register (Offset = 84h) [reset = X]

PLL0_HSDIV_CTRL1 is shown in Figure 5-823 and described in Table 5-1704.

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HSDIV_CTRL1 register for PLL0

Table 5-1703 PLL0_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 0084h

Figure 5-823 PLL0_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1704 PLL0_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.14 PLL0_HSDIV_CTRL2 Register (Offset = 88h) [reset = X]

PLL0_HSDIV_CTRL2 is shown in Figure 5-824 and described in Table 5-1706.

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HSDIV_CTRL2 register for PLL0

Table 5-1705 PLL0_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 0088h

Figure 5-824 PLL0_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1706 PLL0_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.15 PLL0_HSDIV_CTRL3 Register (Offset = 8Ch) [reset = X]

PLL0_HSDIV_CTRL3 is shown in Figure 5-825 and described in Table 5-1708.

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HSDIV_CTRL3 register for PLL0

Table 5-1707 PLL0_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 008Ch

Figure 5-825 PLL0_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1708 PLL0_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.16 PLL0_HSDIV_CTRL4 Register (Offset = 90h) [reset = X]

PLL0_HSDIV_CTRL4 is shown in Figure 5-826 and described in Table 5-1710.

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HSDIV_CTRL4 register for PLL0

Table 5-1709 PLL0_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 0090h

Figure 5-826 PLL0_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1710 PLL0_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.17 PLL0_HSDIV_CTRL5 Register (Offset = 94h) [reset = X]

PLL0_HSDIV_CTRL5 is shown in Figure 5-827 and described in Table 5-1712.

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HSDIV_CTRL5 register for PLL0

Table 5-1711 PLL0_HSDIV_CTRL5 Instances

Instance	Physical Address
PLL0_CFG	0068 0094h

Figure 5-827 PLL0_HSDIV_CTRL5 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1712 PLL0_HSDIV_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.18 PLL0_HSDIV_CTRL6 Register (Offset = 98h) [reset = X]

PLL0_HSDIV_CTRL6 is shown in Figure 5-828 and described in Table 5-1714.

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HSDIV_CTRL6 register for PLL0

Table 5-1713 PLL0_HSDIV_CTRL6 Instances

Instance	Physical Address
PLL0_CFG	0068 0098h

Figure 5-828 PLL0_HSDIV_CTRL6 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1714 PLL0_HSDIV_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.19 PLL0_HSDIV_CTRL7 Register (Offset = 9Ch) [reset = X]

PLL0_HSDIV_CTRL7 is shown in Figure 5-829 and described in Table 5-1716.

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HSDIV_CTRL7 register for PLL0

Table 5-1715 PLL0_HSDIV_CTRL7 Instances

Instance	Physical Address
PLL0_CFG	0068 009Ch

Figure 5-829 PLL0_HSDIV_CTRL7 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1716 PLL0_HSDIV_CTRL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.20 PLL1_PID Register (Offset = 1000h) [reset = 61801001h]

PLL1_PID is shown in Figure 5-830 and described in Table 5-1718.

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Peripheral Identification Register

Table 5-1717 PLL1_PID Instances

Instance	Physical Address
PLL0_CFG	0068 1000h

Figure 5-830 PLL1_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1718 PLL1_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.21 PLL1_CFG Register (Offset = 1008h) [reset = X]

PLL1_CFG is shown in Figure 5-831 and described in Table 5-1720.

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PLL MMR Configuration

Table 5-1719 PLL1_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 1008h

Figure 5-831 PLL1_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-BFh

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-BFh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1720 PLL1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	BFh	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.22 PLL1_LOCKKEY0 Register (Offset = 1010h) [reset = 0h]

PLL1_LOCKKEY0 is shown in Figure 5-832 and described in Table 5-1722.

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PLL1 Lock Key 0 Register

Table 5-1721 PLL1_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 1010h

Figure 5-832 PLL1_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1722 PLL1_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.23 PLL1_LOCKKEY1 Register (Offset = 1014h) [reset = 0h]

PLL1_LOCKKEY1 is shown in Figure 5-833 and described in Table 5-1724.

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PLL1 Lock Key 1 RegisterAddr

Table 5-1723 PLL1_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 1014h

Figure 5-833 PLL1_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1724 PLL1_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

4.6.2.24 PLL1_CTRL Register (Offset = 1020h) [reset = X]

PLL1_CTRL is shown in Figure 5-834 and described in Table 5-1726.

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PLL1 Control

Table 5-1725 PLL1_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1020h

Figure 5-834 PLL1_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1726 PLL1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.25 PLL1_STAT Register (Offset = 1024h) [reset = X]

PLL1_STAT is shown in Figure 5-835 and described in Table 5-1728.

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PLL1 Status

Table 5-1727 PLL1_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 1024h

Figure 5-835 PLL1_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1728 PLL1_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.26 PLL1_FREQ_CTRL0 Register (Offset = 1030h) [reset = X]

PLL1_FREQ_CTRL0 is shown in Figure 5-836 and described in Table 5-1730.

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PLL1 Frequency Control 1 Register

Table 5-1729 PLL1_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 1030h

Figure 5-836 PLL1_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1730 PLL1_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.27 PLL1_FREQ_CTRL1 Register (Offset = 1034h) [reset = X]

PLL1_FREQ_CTRL1 is shown in Figure 5-837 and described in Table 5-1732.

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PLL0 Frequency Control 1 Register

Table 5-1731 PLL1_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 1034h

Figure 5-837 PLL1_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1732 PLL1_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.28 PLL1_DIV_CTRL Register (Offset = 1038h) [reset = X]

PLL1_DIV_CTRL is shown in Figure 5-838 and described in Table 5-1734.

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PLL1 Output Clock Divider Register

Table 5-1733 PLL1_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1038h

Figure 5-838 PLL1_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1734 PLL1_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.29 PLL1_SS_CTRL Register (Offset = 1040h) [reset = X]

PLL1_SS_CTRL is shown in Figure 5-839 and described in Table 5-1736.

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PLL_SS_CTRL register for PLL1

Table 5-1735 PLL1_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 1040h

Figure 5-839 PLL1_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1736 PLL1_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.30 PLL1_SS_SPREAD Register (Offset = 1044h) [reset = X]

PLL1_SS_SPREAD is shown in Figure 5-840 and described in Table 5-1738.

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PLL_SS_SPREAD register for PLL1

Table 5-1737 PLL1_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 1044h

Figure 5-840 PLL1_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1738 PLL1_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.31 PLL1_HSDIV_CTRL0 Register (Offset = 1080h) [reset = X]

PLL1_HSDIV_CTRL0 is shown in Figure 5-841 and described in Table 5-1740.

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HSDIV_CTRL0 register for PLL1

Table 5-1739 PLL1_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 1080h

Figure 5-841 PLL1_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1740 PLL1_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.32 PLL1_HSDIV_CTRL1 Register (Offset = 1084h) [reset = X]

PLL1_HSDIV_CTRL1 is shown in Figure 5-842 and described in Table 5-1742.

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HSDIV_CTRL1 register for PLL1

Table 5-1741 PLL1_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 1084h

Figure 5-842 PLL1_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1742 PLL1_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.33 PLL1_HSDIV_CTRL2 Register (Offset = 1088h) [reset = X]

PLL1_HSDIV_CTRL2 is shown in Figure 5-843 and described in Table 5-1744.

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HSDIV_CTRL2 register for PLL1

Table 5-1743 PLL1_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 1088h

Figure 5-843 PLL1_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1744 PLL1_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.34 PLL1_HSDIV_CTRL3 Register (Offset = 108Ch) [reset = X]

PLL1_HSDIV_CTRL3 is shown in Figure 5-844 and described in Table 5-1746.

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HSDIV_CTRL3 register for PLL1

Table 5-1745 PLL1_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 108Ch

Figure 5-844 PLL1_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1746 PLL1_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.35 PLL1_HSDIV_CTRL4 Register (Offset = 1090h) [reset = X]

PLL1_HSDIV_CTRL4 is shown in Figure 5-845 and described in Table 5-1748.

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HSDIV_CTRL4 register for PLL1

Table 5-1747 PLL1_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 1090h

Figure 5-845 PLL1_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1748 PLL1_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.36 PLL1_HSDIV_CTRL5 Register (Offset = 1094h) [reset = X]

PLL1_HSDIV_CTRL5 is shown in Figure 5-846 and described in Table 5-1750.

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HSDIV_CTRL5 register for PLL1

Table 5-1749 PLL1_HSDIV_CTRL5 Instances

Instance	Physical Address
PLL0_CFG	0068 1094h

Figure 5-846 PLL1_HSDIV_CTRL5 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1750 PLL1_HSDIV_CTRL5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.37 PLL1_HSDIV_CTRL7 Register (Offset = 109Ch) [reset = X]

PLL1_HSDIV_CTRL7 is shown in Figure 5-847 and described in Table 5-1752.

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HSDIV_CTRL7 register for PLL1

Table 5-1751 PLL1_HSDIV_CTRL7 Instances

Instance	Physical Address
PLL0_CFG	0068 109Ch

Figure 5-847 PLL1_HSDIV_CTRL7 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1752 PLL1_HSDIV_CTRL7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.38 PLL2_PID Register (Offset = 2000h) [reset = 61801001h]

PLL2_PID is shown in Figure 5-848 and described in Table 5-1754.

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Peripheral Identification Register

Table 5-1753 PLL2_PID Instances

Instance	Physical Address
PLL0_CFG	0068 2000h

Figure 5-848 PLL2_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1754 PLL2_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.39 PLL2_CFG Register (Offset = 2008h) [reset = X]

PLL2_CFG is shown in Figure 5-849 and described in Table 5-1756.

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PLL MMR Configuration

Table 5-1755 PLL2_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 2008h

Figure 5-849 PLL2_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-5Fh

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-5Fh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1756 PLL2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	5Fh	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.40 PLL2_LOCKKEY0 Register (Offset = 2010h) [reset = 0h]

PLL2_LOCKKEY0 is shown in Figure 5-850 and described in Table 5-1758.

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PLL2 Lock Key 0 Register

Table 5-1757 PLL2_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 2010h

Figure 5-850 PLL2_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1758 PLL2_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.41 PLL2_LOCKKEY1 Register (Offset = 2014h) [reset = 0h]

PLL2_LOCKKEY1 is shown in Figure 5-851 and described in Table 5-1760.

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PLL2 Lock Key 1 RegisterAddr

Table 5-1759 PLL2_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 2014h

Figure 5-851 PLL2_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1760 PLL2_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

4.6.2.42 PLL2_CTRL Register (Offset = 2020h) [reset = X]

PLL2_CTRL is shown in Figure 5-852 and described in Table 5-1762.

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PLL2 Control

Table 5-1761 PLL2_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2020h

Figure 5-852 PLL2_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1762 PLL2_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.43 PLL2_STAT Register (Offset = 2024h) [reset = X]

PLL2_STAT is shown in Figure 5-853 and described in Table 5-1764.

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PLL2 Status

Table 5-1763 PLL2_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 2024h

Figure 5-853 PLL2_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1764 PLL2_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.44 PLL2_FREQ_CTRL0 Register (Offset = 2030h) [reset = X]

PLL2_FREQ_CTRL0 is shown in Figure 5-854 and described in Table 5-1766.

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PLL2 Frequency Control 2 Register

Table 5-1765 PLL2_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 2030h

Figure 5-854 PLL2_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1766 PLL2_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.45 PLL2_FREQ_CTRL1 Register (Offset = 2034h) [reset = X]

PLL2_FREQ_CTRL1 is shown in Figure 5-855 and described in Table 5-1768.

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PLL0 Frequency Control 1 Register

Table 5-1767 PLL2_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 2034h

Figure 5-855 PLL2_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1768 PLL2_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.46 PLL2_DIV_CTRL Register (Offset = 2038h) [reset = X]

PLL2_DIV_CTRL is shown in Figure 5-856 and described in Table 5-1770.

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PLL2 Output Clock Divider Register

Table 5-1769 PLL2_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2038h

Figure 5-856 PLL2_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1770 PLL2_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.47 PLL2_SS_CTRL Register (Offset = 2040h) [reset = X]

PLL2_SS_CTRL is shown in Figure 5-857 and described in Table 5-1772.

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PLL_SS_CTRL register for PLL2

Table 5-1771 PLL2_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 2040h

Figure 5-857 PLL2_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1772 PLL2_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.48 PLL2_SS_SPREAD Register (Offset = 2044h) [reset = X]

PLL2_SS_SPREAD is shown in Figure 5-858 and described in Table 5-1774.

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PLL_SS_SPREAD register for PLL2

Table 5-1773 PLL2_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 2044h

Figure 5-858 PLL2_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1774 PLL2_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.49 PLL2_HSDIV_CTRL0 Register (Offset = 2080h) [reset = X]

PLL2_HSDIV_CTRL0 is shown in Figure 5-859 and described in Table 5-1776.

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HSDIV_CTRL0 register for PLL2

Table 5-1775 PLL2_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 2080h

Figure 5-859 PLL2_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1776 PLL2_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.50 PLL2_HSDIV_CTRL1 Register (Offset = 2084h) [reset = X]

PLL2_HSDIV_CTRL1 is shown in Figure 5-860 and described in Table 5-1778.

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HSDIV_CTRL1 register for PLL2

Table 5-1777 PLL2_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 2084h

Figure 5-860 PLL2_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1778 PLL2_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.51 PLL2_HSDIV_CTRL2 Register (Offset = 2088h) [reset = X]

PLL2_HSDIV_CTRL2 is shown in Figure 5-861 and described in Table 5-1780.

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HSDIV_CTRL2 register for PLL2

Table 5-1779 PLL2_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 2088h

Figure 5-861 PLL2_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1780 PLL2_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.52 PLL2_HSDIV_CTRL3 Register (Offset = 208Ch) [reset = X]

PLL2_HSDIV_CTRL3 is shown in Figure 5-862 and described in Table 5-1782.

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HSDIV_CTRL3 register for PLL2

Table 5-1781 PLL2_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 208Ch

Figure 5-862 PLL2_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1782 PLL2_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.53 PLL2_HSDIV_CTRL4 Register (Offset = 2090h) [reset = X]

PLL2_HSDIV_CTRL4 is shown in Figure 5-863 and described in Table 5-1784.

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HSDIV_CTRL4 register for PLL2

Table 5-1783 PLL2_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 2090h

Figure 5-863 PLL2_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1784 PLL2_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.54 PLL2_HSDIV_CTRL6 Register (Offset = 2098h) [reset = X]

PLL2_HSDIV_CTRL6 is shown in Figure 5-864 and described in Table 5-1786.

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HSDIV_CTRL6 register for PLL2

Table 5-1785 PLL2_HSDIV_CTRL6 Instances

Instance	Physical Address
PLL0_CFG	0068 2098h

Figure 5-864 PLL2_HSDIV_CTRL6 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1786 PLL2_HSDIV_CTRL6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.55 PLL3_PID Register (Offset = 3000h) [reset = 61801001h]

PLL3_PID is shown in Figure 5-865 and described in Table 5-1788.

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Peripheral Identification Register

Table 5-1787 PLL3_PID Instances

Instance	Physical Address
PLL0_CFG	0068 3000h

Figure 5-865 PLL3_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1788 PLL3_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.56 PLL3_CFG Register (Offset = 3008h) [reset = X]

PLL3_CFG is shown in Figure 5-866 and described in Table 5-1790.

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PLL MMR Configuration

Table 5-1789 PLL3_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 3008h

Figure 5-866 PLL3_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-1Fh

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-1Fh

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1790 PLL3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	1Fh	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.57 PLL3_LOCKKEY0 Register (Offset = 3010h) [reset = 0h]

PLL3_LOCKKEY0 is shown in Figure 5-867 and described in Table 5-1792.

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PLL3 Lock Key 0 Register

Table 5-1791 PLL3_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 3010h

Figure 5-867 PLL3_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1792 PLL3_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.58 PLL3_LOCKKEY1 Register (Offset = 3014h) [reset = 0h]

PLL3_LOCKKEY1 is shown in Figure 5-868 and described in Table 5-1794.

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PLL3 Lock Key 1 RegisterAddr

Table 5-1793 PLL3_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 3014h

Figure 5-868 PLL3_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1794 PLL3_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers

4.6.2.59 PLL3_CTRL Register (Offset = 3020h) [reset = X]

PLL3_CTRL is shown in Figure 5-869 and described in Table 5-1796.

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PLL3 Control

Table 5-1795 PLL3_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 3020h

Figure 5-869 PLL3_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1796 PLL3_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.60 PLL3_STAT Register (Offset = 3024h) [reset = X]

PLL3_STAT is shown in Figure 5-870 and described in Table 5-1798.

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PLL3 Status

Table 5-1797 PLL3_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 3024h

Figure 5-870 PLL3_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1798 PLL3_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.61 PLL3_FREQ_CTRL0 Register (Offset = 3030h) [reset = X]

PLL3_FREQ_CTRL0 is shown in Figure 5-871 and described in Table 5-1800.

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PLL3 Frequency Control 3 Register

Table 5-1799 PLL3_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 3030h

Figure 5-871 PLL3_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1800 PLL3_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.62 PLL3_FREQ_CTRL1 Register (Offset = 3034h) [reset = X]

PLL3_FREQ_CTRL1 is shown in Figure 5-872 and described in Table 5-1802.

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PLL0 Frequency Control 1 Register

Table 5-1801 PLL3_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 3034h

Figure 5-872 PLL3_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1802 PLL3_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.63 PLL3_DIV_CTRL Register (Offset = 3038h) [reset = X]

PLL3_DIV_CTRL is shown in Figure 5-873 and described in Table 5-1804.

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PLL3 Output Clock Divider Register

Table 5-1803 PLL3_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 3038h

Figure 5-873 PLL3_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1804 PLL3_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.64 PLL3_SS_CTRL Register (Offset = 3040h) [reset = X]

PLL3_SS_CTRL is shown in Figure 5-874 and described in Table 5-1806.

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PLL_SS_CTRL register for PLL3

Table 5-1805 PLL3_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 3040h

Figure 5-874 PLL3_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1806 PLL3_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.65 PLL3_SS_SPREAD Register (Offset = 3044h) [reset = X]

PLL3_SS_SPREAD is shown in Figure 5-875 and described in Table 5-1808.

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PLL_SS_SPREAD register for PLL3

Table 5-1807 PLL3_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 3044h

Figure 5-875 PLL3_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1808 PLL3_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.66 PLL3_HSDIV_CTRL0 Register (Offset = 3080h) [reset = X]

PLL3_HSDIV_CTRL0 is shown in Figure 5-876 and described in Table 5-1810.

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HSDIV_CTRL0 register for PLL3

Table 5-1809 PLL3_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 3080h

Figure 5-876 PLL3_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1810 PLL3_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.67 PLL3_HSDIV_CTRL1 Register (Offset = 3084h) [reset = X]

PLL3_HSDIV_CTRL1 is shown in Figure 5-877 and described in Table 5-1812.

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HSDIV_CTRL1 register for PLL3

Table 5-1811 PLL3_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 3084h

Figure 5-877 PLL3_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1812 PLL3_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.68 PLL3_HSDIV_CTRL2 Register (Offset = 3088h) [reset = X]

PLL3_HSDIV_CTRL2 is shown in Figure 5-878 and described in Table 5-1814.

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HSDIV_CTRL2 register for PLL3

Table 5-1813 PLL3_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 3088h

Figure 5-878 PLL3_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1814 PLL3_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.69 PLL3_HSDIV_CTRL3 Register (Offset = 308Ch) [reset = X]

PLL3_HSDIV_CTRL3 is shown in Figure 5-879 and described in Table 5-1816.

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HSDIV_CTRL3 register for PLL3

Table 5-1815 PLL3_HSDIV_CTRL3 Instances

Instance	Physical Address
PLL0_CFG	0068 308Ch

Figure 5-879 PLL3_HSDIV_CTRL3 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1816 PLL3_HSDIV_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.70 PLL3_HSDIV_CTRL4 Register (Offset = 3090h) [reset = X]

PLL3_HSDIV_CTRL4 is shown in Figure 5-880 and described in Table 5-1818.

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HSDIV_CTRL4 register for PLL3

Table 5-1817 PLL3_HSDIV_CTRL4 Instances

Instance	Physical Address
PLL0_CFG	0068 3090h

Figure 5-880 PLL3_HSDIV_CTRL4 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1818 PLL3_HSDIV_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.71 PLL4_PID Register (Offset = 4000h) [reset = 61801001h]

PLL4_PID is shown in Figure 5-881 and described in Table 5-1820.

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Peripheral Identification Register

Table 5-1819 PLL4_PID Instances

Instance	Physical Address
PLL0_CFG	0068 4000h

Figure 5-881 PLL4_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1820 PLL4_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.72 PLL4_CFG Register (Offset = 4008h) [reset = X]

PLL4_CFG is shown in Figure 5-882 and described in Table 5-1822.

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PLL MMR Configuration

Table 5-1821 PLL4_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 4008h

Figure 5-882 PLL4_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-7h

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-7h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1822 PLL4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	7h	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.73 PLL4_LOCKKEY0 Register (Offset = 4010h) [reset = 0h]

PLL4_LOCKKEY0 is shown in Figure 5-883 and described in Table 5-1824.

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PLL4 Lock Key 0 Register

Table 5-1823 PLL4_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 4010h

Figure 5-883 PLL4_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1824 PLL4_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.74 PLL4_LOCKKEY1 Register (Offset = 4014h) [reset = 0h]

PLL4_LOCKKEY1 is shown in Figure 5-884 and described in Table 5-1826.

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PLL4 Lock Key 1 RegisterAddr

Table 5-1825 PLL4_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 4014h

Figure 5-884 PLL4_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1826 PLL4_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers

4.6.2.75 PLL4_CTRL Register (Offset = 4020h) [reset = X]

PLL4_CTRL is shown in Figure 5-885 and described in Table 5-1828.

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PLL4 Control

Table 5-1827 PLL4_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 4020h

Figure 5-885 PLL4_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1828 PLL4_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.76 PLL4_STAT Register (Offset = 4024h) [reset = X]

PLL4_STAT is shown in Figure 5-886 and described in Table 5-1830.

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PLL4 Status

Table 5-1829 PLL4_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 4024h

Figure 5-886 PLL4_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1830 PLL4_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.77 PLL4_FREQ_CTRL0 Register (Offset = 4030h) [reset = X]

PLL4_FREQ_CTRL0 is shown in Figure 5-887 and described in Table 5-1832.

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PLL4 Frequency Control 4 Register

Table 5-1831 PLL4_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 4030h

Figure 5-887 PLL4_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1832 PLL4_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.78 PLL4_FREQ_CTRL1 Register (Offset = 4034h) [reset = X]

PLL4_FREQ_CTRL1 is shown in Figure 5-888 and described in Table 5-1834.

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PLL0 Frequency Control 1 Register

Table 5-1833 PLL4_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 4034h

Figure 5-888 PLL4_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1834 PLL4_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.79 PLL4_DIV_CTRL Register (Offset = 4038h) [reset = X]

PLL4_DIV_CTRL is shown in Figure 5-889 and described in Table 5-1836.

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PLL4 Output Clock Divider Register

Table 5-1835 PLL4_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 4038h

Figure 5-889 PLL4_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1836 PLL4_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.80 PLL4_SS_CTRL Register (Offset = 4040h) [reset = X]

PLL4_SS_CTRL is shown in Figure 5-890 and described in Table 5-1838.

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PLL_SS_CTRL register for PLL4

Table 5-1837 PLL4_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 4040h

Figure 5-890 PLL4_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1838 PLL4_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.81 PLL4_SS_SPREAD Register (Offset = 4044h) [reset = X]

PLL4_SS_SPREAD is shown in Figure 5-891 and described in Table 5-1840.

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PLL_SS_SPREAD register for PLL4

Table 5-1839 PLL4_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 4044h

Figure 5-891 PLL4_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1840 PLL4_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.82 PLL4_HSDIV_CTRL0 Register (Offset = 4080h) [reset = X]

PLL4_HSDIV_CTRL0 is shown in Figure 5-892 and described in Table 5-1842.

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HSDIV_CTRL0 register for PLL4

Table 5-1841 PLL4_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 4080h

Figure 5-892 PLL4_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1842 PLL4_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.83 PLL4_HSDIV_CTRL1 Register (Offset = 4084h) [reset = X]

PLL4_HSDIV_CTRL1 is shown in Figure 5-893 and described in Table 5-1844.

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HSDIV_CTRL1 register for PLL4

Table 5-1843 PLL4_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 4084h

Figure 5-893 PLL4_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1844 PLL4_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.84 PLL4_HSDIV_CTRL2 Register (Offset = 4088h) [reset = X]

PLL4_HSDIV_CTRL2 is shown in Figure 5-894 and described in Table 5-1846.

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HSDIV_CTRL2 register for PLL4

Table 5-1845 PLL4_HSDIV_CTRL2 Instances

Instance	Physical Address
PLL0_CFG	0068 4088h

Figure 5-894 PLL4_HSDIV_CTRL2 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1846 PLL4_HSDIV_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.85 PLL7_PID Register (Offset = 7000h) [reset = 61801001h]

PLL7_PID is shown in Figure 5-895 and described in Table 5-1848.

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Peripheral Identification Register

Table 5-1847 PLL7_PID Instances

Instance	Physical Address
PLL0_CFG	0068 7000h

Figure 5-895 PLL7_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1848 PLL7_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.86 PLL7_CFG Register (Offset = 7008h) [reset = X]

PLL7_CFG is shown in Figure 5-896 and described in Table 5-1850.

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PLL MMR Configuration

Table 5-1849 PLL7_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 7008h

Figure 5-896 PLL7_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-1h

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-1h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1850 PLL7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	1h	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.87 PLL7_LOCKKEY0 Register (Offset = 7010h) [reset = 0h]

PLL7_LOCKKEY0 is shown in Figure 5-897 and described in Table 5-1852.

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PLL7 Lock Key 0 Register

Table 5-1851 PLL7_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 7010h

Figure 5-897 PLL7_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1852 PLL7_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.88 PLL7_LOCKKEY1 Register (Offset = 7014h) [reset = 0h]

PLL7_LOCKKEY1 is shown in Figure 5-898 and described in Table 5-1854.

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PLL7 Lock Key 1 RegisterAddr

Table 5-1853 PLL7_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 7014h

Figure 5-898 PLL7_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1854 PLL7_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers

4.6.2.89 PLL7_CTRL Register (Offset = 7020h) [reset = X]

PLL7_CTRL is shown in Figure 5-899 and described in Table 5-1856.

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PLL7 Control

Table 5-1855 PLL7_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 7020h

Figure 5-899 PLL7_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1856 PLL7_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.90 PLL7_STAT Register (Offset = 7024h) [reset = X]

PLL7_STAT is shown in Figure 5-900 and described in Table 5-1858.

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PLL7 Status

Table 5-1857 PLL7_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 7024h

Figure 5-900 PLL7_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1858 PLL7_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.91 PLL7_FREQ_CTRL0 Register (Offset = 7030h) [reset = X]

PLL7_FREQ_CTRL0 is shown in Figure 5-901 and described in Table 5-1860.

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PLL7 Frequency Control 7 Register

Table 5-1859 PLL7_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 7030h

Figure 5-901 PLL7_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1860 PLL7_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.92 PLL7_FREQ_CTRL1 Register (Offset = 7034h) [reset = X]

PLL7_FREQ_CTRL1 is shown in Figure 5-902 and described in Table 5-1862.

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PLL0 Frequency Control 1 Register

Table 5-1861 PLL7_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 7034h

Figure 5-902 PLL7_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1862 PLL7_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.93 PLL7_DIV_CTRL Register (Offset = 7038h) [reset = X]

PLL7_DIV_CTRL is shown in Figure 5-903 and described in Table 5-1864.

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PLL7 Output Clock Divider Register

Table 5-1863 PLL7_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 7038h

Figure 5-903 PLL7_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1864 PLL7_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.94 PLL7_SS_CTRL Register (Offset = 7040h) [reset = X]

PLL7_SS_CTRL is shown in Figure 5-904 and described in Table 5-1866.

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PLL_SS_CTRL register for PLL7

Table 5-1865 PLL7_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 7040h

Figure 5-904 PLL7_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1866 PLL7_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.95 PLL7_SS_SPREAD Register (Offset = 7044h) [reset = X]

PLL7_SS_SPREAD is shown in Figure 5-905 and described in Table 5-1868.

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PLL_SS_SPREAD register for PLL7

Table 5-1867 PLL7_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 7044h

Figure 5-905 PLL7_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1868 PLL7_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.96 PLL7_CAL_CTRL Register (Offset = 7060h) [reset = X]

PLL7_CAL_CTRL is shown in Figure 5-906 and described in Table 5-1870.

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PLL7 Calibration Control Register

Table 5-1869 PLL7_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 7060h

Figure 5-906 PLL7_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1870 PLL7_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	X	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known
19	RESERVED	R	X	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	X	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.97 PLL7_CAL_STAT Register (Offset = 7064h) [reset = X]

PLL7_CAL_STAT is shown in Figure 5-907 and described in Table 5-1872.

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PLL7 Calibration Status Register

Table 5-1871 PLL7_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 7064h

Figure 5-907 PLL7_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-0h

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-0h

7	6	5	4	3	2	1	0
CAL_OUT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1872 PLL7_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	0h	Reserved for future use
30-20	RESERVED	R	X	Reserved
19-16	LOCK_CNT	R	0h	Reserved for future use
15-12	RESERVED	R	X	Reserved
11-0	CAL_OUT	R	0h	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in [11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration

4.6.2.98 PLL7_HSDIV_CTRL0 Register (Offset = 7080h) [reset = X]

PLL7_HSDIV_CTRL0 is shown in Figure 5-908 and described in Table 5-1874.

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HSDIV_CTRL0 register for PLL7

Table 5-1873 PLL7_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 7080h

Figure 5-908 PLL7_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1874 PLL7_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.99 PLL8_PID Register (Offset = 8000h) [reset = 61801001h]

PLL8_PID is shown in Figure 5-909 and described in Table 5-1876.

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Peripheral Identification Register

Table 5-1875 PLL8_PID Instances

Instance	Physical Address
PLL0_CFG	0068 8000h

Figure 5-909 PLL8_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1876 PLL8_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.100 PLL8_CFG Register (Offset = 8008h) [reset = X]

PLL8_CFG is shown in Figure 5-910 and described in Table 5-1878.

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PLL MMR Configuration

Table 5-1877 PLL8_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 8008h

Figure 5-910 PLL8_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-1h

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-1h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1878 PLL8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	1h	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.101 PLL8_LOCKKEY0 Register (Offset = 8010h) [reset = 0h]

PLL8_LOCKKEY0 is shown in Figure 5-911 and described in Table 5-1880.

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PLL8 Lock Key 0 Register

Table 5-1879 PLL8_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 8010h

Figure 5-911 PLL8_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1880 PLL8_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.102 PLL8_LOCKKEY1 Register (Offset = 8014h) [reset = 0h]

PLL8_LOCKKEY1 is shown in Figure 5-912 and described in Table 5-1882.

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PLL8 Lock Key 1 RegisterAddr

Table 5-1881 PLL8_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 8014h

Figure 5-912 PLL8_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1882 PLL8_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers

4.6.2.103 PLL8_CTRL Register (Offset = 8020h) [reset = X]

PLL8_CTRL is shown in Figure 5-913 and described in Table 5-1884.

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PLL8 Control

Table 5-1883 PLL8_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8020h

Figure 5-913 PLL8_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1884 PLL8_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.104 PLL8_STAT Register (Offset = 8024h) [reset = X]

PLL8_STAT is shown in Figure 5-914 and described in Table 5-1886.

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PLL8 Status

Table 5-1885 PLL8_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 8024h

Figure 5-914 PLL8_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1886 PLL8_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.105 PLL8_FREQ_CTRL0 Register (Offset = 8030h) [reset = X]

PLL8_FREQ_CTRL0 is shown in Figure 5-915 and described in Table 5-1888.

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PLL8 Frequency Control 8 Register

Table 5-1887 PLL8_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 8030h

Figure 5-915 PLL8_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1888 PLL8_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.106 PLL8_FREQ_CTRL1 Register (Offset = 8034h) [reset = X]

PLL8_FREQ_CTRL1 is shown in Figure 5-916 and described in Table 5-1890.

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PLL0 Frequency Control 1 Register

Table 5-1889 PLL8_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 8034h

Figure 5-916 PLL8_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1890 PLL8_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.107 PLL8_DIV_CTRL Register (Offset = 8038h) [reset = X]

PLL8_DIV_CTRL is shown in Figure 5-917 and described in Table 5-1892.

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PLL8 Output Clock Divider Register

Table 5-1891 PLL8_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8038h

Figure 5-917 PLL8_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1892 PLL8_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.108 PLL8_SS_CTRL Register (Offset = 8040h) [reset = X]

PLL8_SS_CTRL is shown in Figure 5-918 and described in Table 5-1894.

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PLL_SS_CTRL register for PLL8

Table 5-1893 PLL8_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8040h

Figure 5-918 PLL8_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1894 PLL8_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.109 PLL8_SS_SPREAD Register (Offset = 8044h) [reset = X]

PLL8_SS_SPREAD is shown in Figure 5-919 and described in Table 5-1896.

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PLL_SS_SPREAD register for PLL8

Table 5-1895 PLL8_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 8044h

Figure 5-919 PLL8_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1896 PLL8_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.110 PLL8_CAL_CTRL Register (Offset = 8060h) [reset = X]

PLL8_CAL_CTRL is shown in Figure 5-920 and described in Table 5-1898.

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PLL8 Calibration Control Register

Table 5-1897 PLL8_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 8060h

Figure 5-920 PLL8_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1898 PLL8_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	X	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known
19	RESERVED	R	X	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	X	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.111 PLL8_CAL_STAT Register (Offset = 8064h) [reset = X]

PLL8_CAL_STAT is shown in Figure 5-921 and described in Table 5-1900.

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PLL8 Calibration Status Register

Table 5-1899 PLL8_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 8064h

Figure 5-921 PLL8_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-0h

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-0h

7	6	5	4	3	2	1	0
CAL_OUT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1900 PLL8_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	0h	Reserved for future use
30-20	RESERVED	R	X	Reserved
19-16	LOCK_CNT	R	0h	Reserved for future use
15-12	RESERVED	R	X	Reserved
11-0	CAL_OUT	R	0h	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in [11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration

4.6.2.112 PLL8_HSDIV_CTRL0 Register (Offset = 8080h) [reset = X]

PLL8_HSDIV_CTRL0 is shown in Figure 5-922 and described in Table 5-1902.

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HSDIV_CTRL0 register for PLL8

Table 5-1901 PLL8_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 8080h

Figure 5-922 PLL8_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1902 PLL8_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.113 PLL12_PID Register (Offset = C000h) [reset = 61801001h]

PLL12_PID is shown in Figure 5-923 and described in Table 5-1904.

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Peripheral Identification Register

Table 5-1903 PLL12_PID Instances

Instance	Physical Address
PLL0_CFG	0068 C000h

Figure 5-923 PLL12_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1904 PLL12_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.114 PLL12_CFG Register (Offset = C008h) [reset = X]

PLL12_CFG is shown in Figure 5-924 and described in Table 5-1906.

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PLL MMR Configuration

Table 5-1905 PLL12_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 C008h

Figure 5-924 PLL12_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-1h

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-1h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1906 PLL12_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	1h	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	1h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.115 PLL12_LOCKKEY0 Register (Offset = C010h) [reset = 0h]

PLL12_LOCKKEY0 is shown in Figure 5-925 and described in Table 5-1908.

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PLL12 Lock Key 0 Register

Table 5-1907 PLL12_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 C010h

Figure 5-925 PLL12_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1908 PLL12_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.116 PLL12_LOCKKEY1 Register (Offset = C014h) [reset = 0h]

PLL12_LOCKKEY1 is shown in Figure 5-926 and described in Table 5-1910.

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PLL12 Lock Key 1 RegisterAddr

Table 5-1909 PLL12_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 C014h

Figure 5-926 PLL12_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1910 PLL12_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers

4.6.2.117 PLL12_CTRL Register (Offset = C020h) [reset = X]

PLL12_CTRL is shown in Figure 5-927 and described in Table 5-1912.

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PLL12 Control

Table 5-1911 PLL12_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C020h

Figure 5-927 PLL12_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1912 PLL12_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.118 PLL12_STAT Register (Offset = C024h) [reset = X]

PLL12_STAT is shown in Figure 5-928 and described in Table 5-1914.

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PLL12 Status

Table 5-1913 PLL12_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 C024h

Figure 5-928 PLL12_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1914 PLL12_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.119 PLL12_FREQ_CTRL0 Register (Offset = C030h) [reset = X]

PLL12_FREQ_CTRL0 is shown in Figure 5-929 and described in Table 5-1916.

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PLL12 Frequency Control 12 Register

Table 5-1915 PLL12_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 C030h

Figure 5-929 PLL12_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1916 PLL12_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.120 PLL12_FREQ_CTRL1 Register (Offset = C034h) [reset = X]

PLL12_FREQ_CTRL1 is shown in Figure 5-930 and described in Table 5-1918.

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PLL0 Frequency Control 1 Register

Table 5-1917 PLL12_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 C034h

Figure 5-930 PLL12_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1918 PLL12_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.121 PLL12_DIV_CTRL Register (Offset = C038h) [reset = X]

PLL12_DIV_CTRL is shown in Figure 5-931 and described in Table 5-1920.

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PLL12 Output Clock Divider Register

Table 5-1919 PLL12_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C038h

Figure 5-931 PLL12_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1920 PLL12_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.122 PLL12_SS_CTRL Register (Offset = C040h) [reset = X]

PLL12_SS_CTRL is shown in Figure 5-932 and described in Table 5-1922.

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PLL_SS_CTRL register for PLL12

Table 5-1921 PLL12_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C040h

Figure 5-932 PLL12_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1922 PLL12_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.123 PLL12_SS_SPREAD Register (Offset = C044h) [reset = X]

PLL12_SS_SPREAD is shown in Figure 5-933 and described in Table 5-1924.

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PLL_SS_SPREAD register for PLL12

Table 5-1923 PLL12_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 C044h

Figure 5-933 PLL12_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1924 PLL12_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.124 PLL12_CAL_CTRL Register (Offset = C060h) [reset = X]

PLL12_CAL_CTRL is shown in Figure 5-934 and described in Table 5-1926.

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PLL12 Calibration Control Register

Table 5-1925 PLL12_CAL_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 C060h

Figure 5-934 PLL12_CAL_CTRL Register

31	30	29	28	27	26	25	24
CAL_EN	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			FAST_CAL	RESERVED	CAL_CNT
R-0h			R/W-0h	R-0h	R/W-2h

15	14	13	12	11	10	9	8
CAL_BYP	RESERVED			CAL_IN
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
CAL_IN
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1926 PLL12_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_EN	R/W	0h	Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input
30-21	RESERVED	R	X	Reserved
20	FAST_CAL	R/W	0h	Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known
19	RESERVED	R	X	Reserved
18-16	CAL_CNT	R/W	2h	Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt
15	CAL_BYP	R/W	0h	Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction
14-12	RESERVED	R	X	Reserved
11-0	CAL_IN	R/W	0h	Calibration input When cal_byp is 1'b0, this represents the initial condition for calibration. When cal_byp is 1'b1, this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and negative values delaying the slower path reset.

4.6.2.125 PLL12_CAL_STAT Register (Offset = C064h) [reset = X]

PLL12_CAL_STAT is shown in Figure 5-935 and described in Table 5-1928.

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PLL12 Calibration Status Register

Table 5-1927 PLL12_CAL_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 C064h

Figure 5-935 PLL12_CAL_STAT Register

31	30	29	28	27	26	25	24
CAL_LOCK	RESERVED
R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				LOCK_CNT
R-0h				R-0h

15	14	13	12	11	10	9	8
RESERVED				CAL_OUT
R-0h				R-0h

7	6	5	4	3	2	1	0
CAL_OUT
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1928 PLL12_CAL_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CAL_LOCK	R	0h	Reserved for future use
30-20	RESERVED	R	X	Reserved
19-16	LOCK_CNT	R	0h	Reserved for future use
15-12	RESERVED	R	X	Reserved
11-0	CAL_OUT	R	0h	Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in [11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration

4.6.2.126 PLL12_HSDIV_CTRL0 Register (Offset = C080h) [reset = X]

PLL12_HSDIV_CTRL0 is shown in Figure 5-936 and described in Table 5-1930.

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HSDIV_CTRL0 register for PLL12

Table 5-1929 PLL12_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 C080h

Figure 5-936 PLL12_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1930 PLL12_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.127 PLL14_PID Register (Offset = E000h) [reset = 61801001h]

PLL14_PID is shown in Figure 5-937 and described in Table 5-1932.

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Peripheral Identification Register

Table 5-1931 PLL14_PID Instances

Instance	Physical Address
PLL0_CFG	0068 E000h

Figure 5-937 PLL14_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE
R-1h		R-2h		R-180h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISC					MAJOR			CUSTOM		MINOR
R-2h					R-0h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-1932 PLL14_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral Identification Register Scheme
29-28	BU	R	2h	Business Unit - Processors
27-16	MODULE	R	180h	Module functional identifier
15-11	MISC	R	2h	Misc revision number
10-8	MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	custom revision number
5-0	MINOR	R	1h	Minor revision number

4.6.2.128 PLL14_CFG Register (Offset = E008h) [reset = X]

PLL14_CFG is shown in Figure 5-938 and described in Table 5-1934.

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PLL MMR Configuration

Table 5-1933 PLL14_CFG Instances

Instance	Physical Address
PLL0_CFG	0068 E008h

Figure 5-938 PLL14_CFG Register

31	30	29	28	27	26	25	24
HSDIV_PRSNT
R-3h

23	22	21	20	19	18	17	16
HSDIV_PRSNT
R-3h

15	14	13	12	11	10	9	8
RESERVED			SSM_TYPE		RESERVED		SSM_WVTBL
R-0h			R-1h		R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						PLL_TYPE
R-0h						R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1934 PLL14_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HSDIV_PRSNT	R	3h	High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock
15-13	RESERVED	R	X	Reserved
12-11	SSM_TYPE	R	1h	Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved
10-9	RESERVED	R	X	Reserved
8	SSM_WVTBL	R	0h	Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present
7-2	RESERVED	R	X	Reserved
1-0	PLL_TYPE	R	0h	Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL

4.6.2.129 PLL14_LOCKKEY0 Register (Offset = E010h) [reset = 0h]

PLL14_LOCKKEY0 is shown in Figure 5-939 and described in Table 5-1936.

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PLL14 Lock Key 0 Register

Table 5-1935 PLL14_LOCKKEY0 Instances

Instance	Physical Address
PLL0_CFG	0068 E010h

Figure 5-939 PLL14_LOCKKEY0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1936 PLL14_LOCKKEY0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers
0	UNLOCKED	R	0h	Unlock status. When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

4.6.2.130 PLL14_LOCKKEY1 Register (Offset = E014h) [reset = 0h]

PLL14_LOCKKEY1 is shown in Figure 5-940 and described in Table 5-1938.

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PLL14 Lock Key 1 RegisterAddr

Table 5-1937 PLL14_LOCKKEY1 Instances

Instance	Physical Address
PLL0_CFG	0068 E014h

Figure 5-940 PLL14_LOCKKEY1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOCKKEY1_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1938 PLL14_LOCKKEY1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOCKKEY1_VAL	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition14 registers

4.6.2.131 PLL14_CTRL Register (Offset = E020h) [reset = X]

PLL14_CTRL is shown in Figure 5-941 and described in Table 5-1940.

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PLL14 Control

Table 5-1939 PLL14_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E020h

Figure 5-941 PLL14_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED
R/W-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED							BYP_ON_LOCKLOSS
R-0h							R/W-1h

15	14	13	12	11	10	9	8
PLL_EN	RESERVED						INTL_BYP_EN
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CLK_4PH_EN	CLK_POSTDIV_EN	RESERVED		DSM_EN	DAC_EN
R-0h		R/W-0h	R/W-1h	R-0h		R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1940 PLL14_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs
30-17	RESERVED	R	X	Reserved
16	BYP_ON_LOCKLOSS	R/W	1h	Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock
15	PLL_EN	R/W	0h	PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled
14-9	RESERVED	R	X	Reserved
8	INTL_BYP_EN	R/W	0h	PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock
7-6	RESERVED	R	X	Reserved
5	CLK_4PH_EN	R/W	0h	Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled.
4	CLK_POSTDIV_EN	R/W	1h	Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled.
3-2	RESERVED	R	X	Reserved
1	DSM_EN	R/W	0h	Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)
0	DAC_EN	R/W	1h	Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode)

4.6.2.132 PLL14_STAT Register (Offset = E024h) [reset = X]

PLL14_STAT is shown in Figure 5-942 and described in Table 5-1942.

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PLL14 Status

Table 5-1941 PLL14_STAT Instances

Instance	Physical Address
PLL0_CFG	0068 E024h

Figure 5-942 PLL14_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							LOCK
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-1942 PLL14_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	LOCK	R	0h	PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked

4.6.2.133 PLL14_FREQ_CTRL0 Register (Offset = E030h) [reset = X]

PLL14_FREQ_CTRL0 is shown in Figure 5-943 and described in Table 5-1944.

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PLL14 Frequency Control 14 Register

Table 5-1943 PLL14_FREQ_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 E030h

Figure 5-943 PLL14_FREQ_CTRL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				FB_DIV_INT
R-0h																				R/W-10h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1944 PLL14_FREQ_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	FB_DIV_INT	R/W	10h	PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported

4.6.2.134 PLL14_FREQ_CTRL1 Register (Offset = E034h) [reset = X]

PLL14_FREQ_CTRL1 is shown in Figure 5-944 and described in Table 5-1946.

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PLL0 Frequency Control 1 Register

Table 5-1945 PLL14_FREQ_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 E034h

Figure 5-944 PLL14_FREQ_CTRL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								FB_DIV_FRAC
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1946 PLL14_FREQ_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	FB_DIV_FRAC	R/W	0h	PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2²⁴)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2²⁴)) 24'h000002 - .000000119209 (2/(2²⁴)) : 24'h800000 - . 500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2²⁴))

4.6.2.135 PLL14_DIV_CTRL Register (Offset = E038h) [reset = X]

PLL14_DIV_CTRL is shown in Figure 5-945 and described in Table 5-1948.

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PLL14 Output Clock Divider Register

Table 5-1947 PLL14_DIV_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E038h

Figure 5-945 PLL14_DIV_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					POST_DIV2			RESERVED					POST_DIV1
R-0h					R/W-1h			R-0h					R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										REF_DIV
R-0h										R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1948 PLL14_DIV_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	X	Reserved
26-24	POST_DIV2	R/W	1h	Secondary post divider. Supports values of 1-7
23-19	RESERVED	R	X	Reserved
18-16	POST_DIV1	R/W	2h	Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7
15-6	RESERVED	R	X	Reserved
5-0	REF_DIV	R/W	1h	Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63

4.6.2.136 PLL14_SS_CTRL Register (Offset = E040h) [reset = X]

PLL14_SS_CTRL is shown in Figure 5-946 and described in Table 5-1950.

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PLL_SS_CTRL register for PLL14

Table 5-1949 PLL14_SS_CTRL Instances

Instance	Physical Address
PLL0_CFG	0068 E040h

Figure 5-946 PLL14_SS_CTRL Register

31	30	29	28	27	26	25	24
BYPASS_EN	RESERVED					WV_TBLE_MAXADDR
R/W-1h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
WV_TBLE_MAXADDR						RESERVED
R/W-0h						R-0h

15	14	13	12	11	10	9	8
RESET	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			DOWNSPREAD_EN	RESERVED			WAVE_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1950 PLL14_SS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_EN	R/W	1h	Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency
30-26	RESERVED	R	X	Reserved
25-18	WV_TBLE_MAXADDR	R/W	0h	Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0
17-16	RESERVED	R	X	Reserved
15	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in reset
14-5	RESERVED	R	X	Reserved
4	DOWNSPREAD_EN	R/W	0h	Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread
3-1	RESERVED	R	X	Reserved
0	WAVE_SEL	R/W	0h	Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table

4.6.2.137 PLL14_SS_SPREAD Register (Offset = E044h) [reset = X]

PLL14_SS_SPREAD is shown in Figure 5-947 and described in Table 5-1952.

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PLL_SS_SPREAD register for PLL14

Table 5-1951 PLL14_SS_SPREAD Instances

Instance	Physical Address
PLL0_CFG	0068 E044h

Figure 5-947 PLL14_SS_SPREAD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MOD_DIV
R-0h												R/W-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											SPREAD
R-0h											R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1952 PLL14_SS_SPREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X	Reserved
19-16	MOD_DIV	R/W	1h	Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63
15-5	RESERVED	R	X	Reserved
4-0	SPREAD	R/W	1h	Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%

4.6.2.138 PLL14_HSDIV_CTRL0 Register (Offset = E080h) [reset = X]

PLL14_HSDIV_CTRL0 is shown in Figure 5-948 and described in Table 5-1954.

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HSDIV_CTRL0 register for PLL14

Table 5-1953 PLL14_HSDIV_CTRL0 Instances

Instance	Physical Address
PLL0_CFG	0068 E080h

Figure 5-948 PLL14_HSDIV_CTRL0 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1954 PLL14_HSDIV_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127

4.6.2.139 PLL14_HSDIV_CTRL1 Register (Offset = E084h) [reset = X]

PLL14_HSDIV_CTRL1 is shown in Figure 5-949 and described in Table 5-1956.

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HSDIV_CTRL1 register for PLL14

Table 5-1955 PLL14_HSDIV_CTRL1 Instances

Instance	Physical Address
PLL0_CFG	0068 E084h

Figure 5-949 PLL14_HSDIV_CTRL1 Register

31	30	29	28	27	26	25	24
RESET	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
CLKOUT_EN	RESERVED						SYNC_DIS
R/W-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	HSDIV
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1956 PLL14_HSDIV_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESET	R/W	0h	SSM reset. When set to 1 the SSM modulator is in resetl
30-16	RESERVED	R	X	Reserved
15	CLKOUT_EN	R/W	0h	CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1
14-9	RESERVED	R	X	Reserved
8	SYNC_DIS	R/W	0h	Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous
7	RESERVED	R	X	Reserved
6-0	HSDIV	R/W	0h	CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127